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[test] fixed a bug

This commit is contained in:
tangxifan 2023-09-25 19:28:19 -07:00
parent 663c9c9fa1
commit a4f53c64c6
1 changed files with 1 additions and 1 deletions
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openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClkMergeSubtilePort_registerable_io_cc_openfpga.xml
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@ -179,7 +179,7 @@
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<tile_annotations>
<merge_subtile_ports tile="io" port="clk"/>
<merge_subtile_ports tile="io_hybrid" port="clk"/>
<global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk" x="-1" y="-1"/>
<tile name="io" port="clk" x="-1" y="-1"/>