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[test] fixed the bug in single-mode lut testcase

This commit is contained in:
tangxifan 2023-11-14 09:35:26 -08:00
parent d108284105
commit 0b473e3454
2 changed files with 2 additions and 2 deletions
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2
openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf
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@ -19,7 +19,7 @@ fpga_flow=vpr_blif
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_device_layout=auto
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml

2
openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
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@ -67,7 +67,7 @@
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout tileable="true">
<layout tileable="true" opin2all_sides="true" concat_wire="true" concat_pass_wire="false">
<auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>