From 0b473e345452e655c26b4275c12cb7a6f31b440c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 14 Nov 2023 09:35:26 -0800
Subject: [PATCH] [test] fixed the bug in single-mode lut testcase

---
 .../tasks/fpga_verilog/lut_design/single_mode/config/task.conf  | 2 +-
 openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml                 | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf
index 989f8e09a..ae5896549 100644
--- a/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf
@@ -19,7 +19,7 @@ fpga_flow=vpr_blif
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
-openfpga_vpr_device_layout=2x2
+openfpga_vpr_device_layout=auto
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
diff --git a/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
index 4706bb30f..634dacd64 100644
--- a/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
@@ -67,7 +67,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="true">
+  <layout tileable="true" opin2all_sides="true" concat_wire="true" concat_pass_wire="false">
     <auto_layout aspect_ratio="1.0">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>