[HDL] Bug fix in Verilog syntax

2021-06-22 16:18:46 -06:00 · 2021-06-22 16:18:46 -06:00 · 0a0d10b36d
parent 4421dfcbbd
commit 0a0d10b36d
1 changed files with 1 additions and 1 deletions
--- a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v
+++ b/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v
@ -10,7 +10,7 @@ module counter (
 );

 	input clk;
-	input reset;
+	input resetb;
 	output [127:0] result;

 	reg [127:0] result;