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[Test] Deply new test to regression test

This commit is contained in:
tangxifan 2021-04-24 15:55:05 -06:00
parent 5adffad602
commit b7da22501c
1 changed files with 3 additions and 0 deletions
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openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
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@ -47,6 +47,9 @@ run-task fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
echo -e "Testing Verilog generation with heterogeneous fabric using 8-bit single-mode multipliers ";
run-task fpga_verilog/dsp/single_mode_mult_8x8 --debug --show_thread_logs
echo -e "Testing Verilog generation with heterogeneous fabric using 16-bit multi-mode multipliers ";
run-task fpga_verilog/dsp/multi_mode_mult_16x16 --debug --show_thread_logs
echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
run-task fpga_verilog/io/multi_io_capacity --debug --show_thread_logs