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Merge branch 'master' into verilog_testbench

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35
docs/source/manual/fpga_verilog/testbench.rst
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@ -58,8 +58,8 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
.. _fig_verilog_testbench_hierarchy:
.. figure:: ./figures/verilog_testbench_hierarchy.png
:scale: 90%
.. figure:: ./figures/verilog_testbench_hierarchy.svg
:scale: 100%
Hierarchy of Verilog testbenches for a FPGA fabric implemented with an application
@ -73,37 +73,6 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
.. note:: Fabric Verilog netlists are included in this file.
.. option:: define_simulation.v
This file includes pre-processing flags required by the testbenches, to smooth HDL simulation.
It will include the folliwng pre-procesing flags:
- ```define AUTOCHECK_SIMULATION`` When enabled, testbench will include self-testing features. The FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag.
.. note:: OpenFPGA always enable the self-testing feature. Users can disable it by commenting out the associated line in the ``define_simulation.v``.
- ```define ENABLE_FORMAL_VERFICATION`` When enabled, the ``<bench_name>_include_netlist.v`` will include the pre-configured FPGA netlist for formal verification usage. This flag is added when ``--print_formal_verification_top_netlist`` option is enabled when calling the ``write_verilog_testbench`` command.
- ```define ENABLE_FORMAL_SIMULATION`` When enabled, the ``<bench_name>_include_netlist.v`` will include the testbench netlist for formal-oriented simulation. This flag is added when ``--print_preconfig_top_testbench`` option is enabled when calling the ``write_verilog_testbench`` command.
.. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled!
- ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_verilog_testbench`` command.
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
- ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_verilog_testbench`` command.
.. warning:: Please disable this flag if you are not using icarus iVerilog simulator.
__ iverilog_website_
.. _iverilog_website: http://iverilog.icarus.com/
.. option:: <bench_name>_autocheck_top_tb.v
This is the netlist for full testbench.

54
docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
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@ -24,14 +24,6 @@ write_fabric_verilog
Output timing information to Verilog netlists for primitive modules
.. option:: --include_signal_init
Output signal initialization to Verilog netlists for primitive modules
.. option:: --support_icarus_simulator
Output Verilog netlists with syntax that iVerilog simulatorcan accept
.. option:: --print_user_defined_template
Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists
@ -59,7 +51,9 @@ write_full_testbench
.. option:: --reference_benchmark_file_path <string>
Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
.. note:: If not specified, the testbench will not include any self-checking feature!
.. option:: --pin_constraints_file <string> or -pcf <string>
@ -84,6 +78,11 @@ write_full_testbench
Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
.. option:: --verbose
Show verbose log
@ -114,9 +113,25 @@ write_preconfigured_fabric_wrapper
Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
.. option:: --support_icarus_simulator
.. option:: --embed_bitstream <string>
Output Verilog netlists with syntax that iVerilog simulator can accept
Specify if the bitstream should be embedded to the Verilog netlists in HDL codes. Available options are ``none``, ``iverilog`` and ``modelsim``. Default value: ``modelsim``.
.. warning:: If the option ``none`` is selected, bitstream will not be embedded. Users should force the bitstream through HDL simulator commands. Otherwise, functionality of the wrapper netlist is wrong!
.. warning:: Please specify ``iverilog`` if you are using icarus iVerilog simulator.
__ iverilog_website_
.. _iverilog_website: http://iverilog.icarus.com/
.. option:: --include_signal_init
Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
.. option:: --verbose
@ -137,7 +152,9 @@ write_preconfigured_testbench
.. option:: --reference_benchmark_file_path <string>
Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
.. note:: If not specified, the testbench will not include any self-checking feature!
.. option:: --pin_constraints_file <string> or -pcf <string>
@ -152,11 +169,6 @@ write_preconfigured_testbench
Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
.. option:: --support_icarus_simulator
Output Verilog netlists with syntax that iVerilog simulator can accept
.. option:: --verbose
Show verbose log
@ -178,6 +190,14 @@ write_simulation_task_info
Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
.. option:: --testbench_type <string>
Specify the type of testbenches [``preconfigured_testbench``|``full_testbench``]. By default, it is the ``preconfigured_testbench``.
.. option:: --time_unit <string>
Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``ms``).
.. option:: --verbose
Show verbose log

43
openfpga/src/base/openfpga_verilog.cpp
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@ -8,6 +8,9 @@
/* Headers from openfpgashell library */
#include "command_exit_codes.h"
/* Headers from openfpgautil library */
#include "openfpga_scale.h"
#include "verilog_api.h"
#include "openfpga_verilog.h"
@ -127,7 +130,8 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -138,12 +142,17 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
options.set_print_formal_verification_top_netlist(true);
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
}
if (true == cmd_context.option_enable(cmd, opt_embed_bitstream)) {
options.set_embedded_bitstream_hdl_type(cmd_context.option_value(cmd, opt_embed_bitstream));
}
/* If pin constraints are enabled by command options, read the file */
PinConstraints pin_constraints;
if (true == cmd_context.option_enable(cmd, opt_pcf)) {
@ -173,7 +182,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_verbose = cmd.option("verbose");
@ -185,7 +193,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_preconfig_top_testbench(true);
@ -217,6 +224,8 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_file = cmd.option("file");
CommandOptionId opt_hdl_dir = cmd.option("hdl_dir");
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_tb_type = cmd.option("testbench_type");
CommandOptionId opt_time_unit = cmd.option("time_unit");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -228,6 +237,32 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx,
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_file));
if (true == cmd_context.option_enable(cmd, opt_time_unit)) {
options.set_time_unit(string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit)));
}
/* Identify testbench type */
std::string full_tb_tag("full_testbench");
std::string preconfig_tb_tag("preconfigured_testbench");
if (true == cmd_context.option_enable(cmd, opt_tb_type)) {
if (std::string("preconfigured_testbench") == cmd_context.option_value(cmd, opt_tb_type)) {
options.set_print_preconfig_top_testbench(true);
} else if (std::string("full_testbench") == cmd_context.option_value(cmd, opt_tb_type)) {
options.set_print_preconfig_top_testbench(false);
options.set_print_top_testbench(true);
} else {
/* Invalid option, error out */
VTR_LOG_ERROR("Invalid option value for testbench type: '%s'! Should be either '%s' or '%s'\n",
cmd_context.option_value(cmd, opt_tb_type).c_str(),
full_tb_tag.c_str(),
preconfig_tb_tag.c_str());
return CMD_EXEC_FATAL_ERROR;
}
} else {
/* Deposit default type which is the preconfigured testbench */
options.set_print_preconfig_top_testbench(true);
}
return fpga_verilog_simulation_task_info(openfpga_ctx.module_graph(),
openfpga_ctx.bitstream_manager(),
g_vpr_ctx.atom(),

28
openfpga/src/base/openfpga_verilog_command.cpp
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@ -84,7 +84,7 @@ ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell<Openfpg
shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING);
/* add an option '--reference_benchmark_file_path'*/
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "specify the file path to the reference verilog netlist");
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "specify the file path to the reference verilog netlist. If specified, the testbench will include self-checking codes");
shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
/* add an option '--fast_configuration' */
@ -97,6 +97,9 @@ ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell<Openfpg
CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
/* Add an option '--no_self_checking' */
shell_cmd.add_option("no_self_checking", false, "Do not generate self-checking codes for Verilog testbenches.");
/* add an option '--include_signal_init' */
shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
@ -146,8 +149,12 @@ ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga:
CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
/* Add an option '--support_icarus_simulator' */
shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator");
/* Add an option '--embed_bitstream' */
CommandOptionId embed_bitstream_opt = shell_cmd.add_option("embed_bitstream", false, "Embed bitstream to the Verilog wrapper netlist; This may cause a large netlist file size");
shell_cmd.set_option_require_value(embed_bitstream_opt, openfpga::OPT_STRING);
/* add an option '--include_signal_init' */
shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
/* add an option '--verbose' */
shell_cmd.add_option("verbose", false, "enable verbose output");
@ -189,12 +196,9 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel
shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING);
/* Add an option '--reference_benchmark_file_path'*/
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "Specify the file path to the reference Verilog netlist. If specified, the testbench will include self-checking codes");
shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
/* Add an option '--support_icarus_simulator' */
shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator");
/* Add an option '--explicit_port_mapping' */
shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
@ -237,9 +241,17 @@ ShellCommandId add_openfpga_write_simulation_task_info_command(openfpga::Shell<O
shell_cmd.set_option_require_value(hdl_dir_opt, openfpga::OPT_STRING);
/* Add an option '--reference_benchmark_file_path'*/
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "Specify the file path to the reference Verilog netlist. If specified, the testbench will include self-checking codes");
shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
/* Add an option '--testbench_type'*/
CommandOptionId tb_type_opt = shell_cmd.add_option("testbench_type", false, "Specify the type of testbenches to be considered. Different testbenches have different simulation parameters.");
shell_cmd.set_option_require_value(tb_type_opt, openfpga::OPT_STRING);
/* Add an option '--time_unit' */
CommandOptionId time_unit_opt = shell_cmd.add_option("time_unit", false, "Specify the time unit to be used in HDL simulation. Acceptable is [a|f|p|n|u|m|k|M]s");
shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");

4
openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
View File

@ -103,7 +103,7 @@ void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
VTR_ASSERT(!sink_instance_name.empty());
/* Get the input id that is used! Disable the unused inputs! */
fp << "set_disable_timing ";
fp << parent_instance_name;
fp << parent_instance_name << "/";
fp << sink_instance_name << "/";
fp << generate_sdc_port(sink_port);
fp << std::endl;
@ -228,7 +228,7 @@ void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
VTR_ASSERT(!sink_instance_name.empty());
/* Get the input id that is used! Disable the unused inputs! */
fp << "set_disable_timing ";
fp << parent_instance_name;
fp << parent_instance_name << "/";
fp << sink_instance_name << "/";
fp << generate_sdc_port(sink_port);
fp << std::endl;

16
openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
View File

@ -83,7 +83,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
t_pb_graph_node* des_pb_graph_node = des_pb_graph_pin->parent_node;
/* Find the src module in module manager */
std::string src_module_name = generate_physical_block_module_name(src_pb_graph_pin->parent_node->pb_type);
std::string src_module_name = generate_physical_block_module_name(src_pb_graph_node->pb_type);
ModuleId src_module = module_manager.find_module(src_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(src_module));
@ -104,6 +104,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
src_instance_name += std::to_string(instance_id);
src_instance_name += "_";
} else {
VTR_ASSERT_SAFE(true == module_manager.instance_name(parent_module, src_module, instance_id).empty());
src_instance_name += module_manager.instance_name(parent_module, src_module, instance_id);
}
}
@ -113,7 +114,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
src_port.set_width(src_pb_graph_pin->pin_number, src_pb_graph_pin->pin_number);
/* Find the des module in module manager */
std::string des_module_name = generate_physical_block_module_name(des_pb_graph_pin->parent_node->pb_type);
std::string des_module_name = generate_physical_block_module_name(des_pb_graph_node->pb_type);
ModuleId des_module = module_manager.find_module(des_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(des_module));
ModulePortId des_module_port_id = module_manager.find_module_port(des_module, generate_pb_type_port_name(des_pb_graph_pin->port));
@ -133,6 +134,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
des_instance_name += std::to_string(instance_id);
des_instance_name += "_";
} else {
VTR_ASSERT_SAFE(true != module_manager.instance_name(parent_module, des_module, instance_id).empty());
des_instance_name += module_manager.instance_name(parent_module, des_module, instance_id);
}
}
@ -150,17 +152,11 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
/* Give full path if hierarchical is not enabled */
std::string src_module_path = src_instance_name;
if (false == hierarchical) {
if (true == src_instance_name.empty()) {
src_instance_name = generate_instance_name(src_module_name, 0);
}
src_module_path = module_path + src_instance_name;
}
std::string des_module_path = des_instance_name;
if (false == hierarchical) {
if (true == des_instance_name.empty()) {
des_instance_name = generate_instance_name(des_module_name, 0);
}
des_module_path = module_path + des_instance_name;
}
@ -521,7 +517,7 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
time_unit,
hierarchical,
format_dir_path(module_path + std::string(physical_mode->pb_type_children[ipb].name)),
format_dir_path(module_path + generate_physical_block_instance_name(&(physical_mode->pb_type_children[ipb]), ipb)),
module_manager,
device_annotation,
&(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]),
@ -582,6 +578,7 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
std::string module_path = format_dir_path(root_path + grid_module_name);
module_path = format_dir_path(module_path + generate_physical_block_instance_name(pb_graph_head->pb_type, pb_graph_head->placement_index));
rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
time_unit,
@ -603,6 +600,7 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
std::string module_path = format_dir_path(root_path + grid_module_name);
module_path = format_dir_path(module_path + generate_physical_block_instance_name(pb_graph_head->pb_type, pb_graph_head->placement_index));
rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
time_unit,

27
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -170,10 +170,6 @@ int fpga_verilog_full_testbench(const ModuleManager &module_manager,
/* Create directories */
create_directory(src_dir_path);
/* Output preprocessing flags for HDL simulations */
print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
options);
/* Generate full testbench for verification, including configuration phase and operating phase */
std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
print_verilog_full_testbench(module_manager,
@ -192,10 +188,11 @@ int fpga_verilog_full_testbench(const ModuleManager &module_manager,
options);
/* Generate a Verilog file including all the netlists that have been generated */
print_verilog_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path());
print_verilog_full_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path(),
options.no_self_checking());
return status;
}
@ -269,10 +266,6 @@ int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager,
/* Create directories */
create_directory(src_dir_path);
/* Output preprocessing flags for HDL simulations */
print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
options);
/* Generate top-level testbench using random vectors */
std::string random_top_testbench_file_path = src_dir_path + netlist_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
print_verilog_random_top_testbench(netlist_name,
@ -286,10 +279,11 @@ int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager,
options);
/* Generate a Verilog file including all the netlists that have been generated */
print_verilog_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path());
print_verilog_preconfigured_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path(),
options.no_self_checking());
return status;
}
@ -323,6 +317,7 @@ int fpga_verilog_simulation_task_info(const ModuleManager &module_manager,
std::string simulation_ini_file_name = options.simulation_ini_path();
VTR_ASSERT(true != options.simulation_ini_path().empty());
print_verilog_simulation_info(simulation_ini_file_name,
options,
netlist_name,
src_dir_path,
atom_ctx, place_ctx, io_location_map,

147
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
View File

@ -90,14 +90,15 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
/********************************************************************
* Print a file that includes all the netlists
* including the fabric netlists and testbenches
* including the fabric netlists and full testbenches
* that have been generated and user-defined.
* Some netlists are open to compile under specific preprocessing flags
*******************************************************************/
void print_verilog_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file) {
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
/* Create the file stream */
@ -110,11 +111,52 @@ void print_verilog_testbench_include_netlists(const std::string& src_dir,
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"));
/* Print preprocessing flags */
print_verilog_comment(fp, std::string("------ Include simulation defines -----"));
print_verilog_include_netlist(fp, src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME));
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
if (true == fabric_netlist_file.empty()) {
print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME));
} else {
VTR_ASSERT_SAFE(false == fabric_netlist_file.empty());
print_verilog_include_netlist(fp, fabric_netlist_file);
}
fp << std::endl;
/* Include reference benchmark netlist only when auto-check flag is enabled */
if (!no_self_checking) {
print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
fp << std::endl;
}
/* Include top-level testbench only when auto-check flag is enabled */
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
/* Close the file stream */
fp.close();
}
/********************************************************************
* Print a file that includes all the netlists
* including the fabric netlists and preconfigured testbenches
* that have been generated and user-defined.
* Some netlists are open to compile under specific preprocessing flags
*******************************************************************/
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
/* Validate the file stream */
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"));
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
if (true == fabric_netlist_file.empty()) {
@ -126,34 +168,16 @@ void print_verilog_testbench_include_netlists(const std::string& src_dir,
fp << std::endl;
/* Include reference benchmark netlist only when auto-check flag is enabled */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
fp << "\t";
print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
print_verilog_endif(fp);
fp << std::endl;
if (!no_self_checking) {
print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
fp << std::endl;
}
/* Include formal verification netlists only when formal verification flag is enable */
print_verilog_preprocessing_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG));
fp << "\t";
/* Include formal verification netlists */
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX));
/* Include formal verification testbench only when formal simulation flag is enabled */
fp << "\t";
print_verilog_preprocessing_flag(fp, std::string(FORMAL_SIMULATION_FLAG));
fp << "\t\t";
/* Include formal verification testbench */
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
fp << "\t";
print_verilog_endif(fp);
print_verilog_endif(fp);
fp << std::endl;
/* Include top-level testbench only when auto-check flag is enabled */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
fp << "\t";
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
print_verilog_endif(fp);
fp << std::endl;
/* Close the file stream */
fp.close();
@ -188,63 +212,4 @@ void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
fp.close();
}
/********************************************************************
* Print a Verilog file containing simulation-related preprocessing flags
*******************************************************************/
void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
const VerilogTestbenchOption& verilog_testbench_opts) {
std::string verilog_fname = src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME);
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
/* Validate the file stream */
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features"));
/* To enable signal initialization */
if (true == verilog_testbench_opts.include_signal_init()) {
print_verilog_define_flag(fp, std::string(VERILOG_SIGNAL_INIT_PREPROC_FLAG), 1);
fp << std::endl;
}
/* To enable functional verfication with Icarus */
if (true == verilog_testbench_opts.support_icarus_simulator()) {
print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1);
fp << std::endl;
}
/* To enable manualy checked simulation */
if (true == verilog_testbench_opts.print_top_testbench()) {
print_verilog_define_flag(fp, std::string(INITIAL_SIMULATION_FLAG), 1);
fp << std::endl;
}
/* To enable auto-checked simulation */
if ( (true == verilog_testbench_opts.print_preconfig_top_testbench())
|| (true == verilog_testbench_opts.print_top_testbench()) ) {
print_verilog_define_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG), 1);
fp << std::endl;
}
/* To enable pre-configured FPGA simulation */
if (true == verilog_testbench_opts.print_formal_verification_top_netlist()) {
print_verilog_define_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG), 1);
fp << std::endl;
}
/* To enable pre-configured FPGA simulation */
if (true == verilog_testbench_opts.print_preconfig_top_testbench()) {
print_verilog_define_flag(fp, std::string(FORMAL_SIMULATION_FLAG), 1);
fp << std::endl;
}
/* Close the file stream */
fp.close();
}
} /* end namespace openfpga */

18
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
View File

@ -21,17 +21,21 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
const std::string& src_dir,
const CircuitLibrary& circuit_lib);
void print_verilog_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file);
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking);
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking);
void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
const FabricVerilogOption& fabric_verilog_opts);
void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
const VerilogTestbenchOption& verilog_testbench_opts);
} /* end namespace openfpga */
#endif

11
openfpga/src/fpga_verilog/verilog_constants.h
View File

@ -7,18 +7,8 @@ constexpr char* VERILOG_NETLIST_FILE_POSTFIX = ".v";
constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns
constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation
constexpr char* VERILOG_SIGNAL_INIT_PREPROC_FLAG = "ENABLE_SIGNAL_INITIALIZATION"; // the flag to enable signal initialization during compilation
constexpr char* VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation
constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to enable initial functional verification
constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification
constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification
constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
// Icarus variables and flag
constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
// End of Icarus variables and flag
constexpr char* FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME = "fabric_netlists.v";
constexpr char* TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
constexpr char* VERILOG_TOP_POSTFIX = "_top.v";
@ -27,7 +17,6 @@ constexpr char* TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_top_tb.v"; /* !!! must be
constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_autocheck_top_tb.v"; /* !!! must be consist with the modelsim_autocheck_testbench_module_postfix */
constexpr char* RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_formal_random_top_tb.v";
constexpr char* DEFINES_VERILOG_FILE_NAME = "fpga_defines.v";
constexpr char* DEFINES_VERILOG_SIMULATION_FILE_NAME = "define_simulation.v";
constexpr char* SUBMODULE_VERILOG_FILE_NAME = "sub_module.v";
constexpr char* LOGIC_BLOCK_VERILOG_FILE_NAME = "logic_blocks.v";
constexpr char* LUTS_VERILOG_FILE_NAME = "luts.v";

70
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -41,7 +41,6 @@ constexpr char* BENCHMARK_INSTANCE_NAME = "REF_DUT";
constexpr char* FPGA_INSTANCE_NAME = "FPGA_DUT";
constexpr char* ERROR_COUNTER = "nb_error";
constexpr char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start";
constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200;
/********************************************************************
* Print the module ports for the Verilog testbench
@ -58,12 +57,12 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
const std::vector<std::string>& clock_port_names,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const e_verilog_default_net_type& default_net_type) {
const VerilogTestbenchOption& options) {
/* Validate the file stream */
valid_file_stream(fp);
print_verilog_default_net_type_declaration(fp,
default_net_type);
options.default_net_type());
/* Print the declaration for the module */
fp << "module " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ";" << std::endl;
@ -85,16 +84,17 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
std::string(BENCHMARK_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX),
std::string(CHECKFLAG_PORT_POSTFIX),
std::string(AUTOCHECKED_SIMULATION_FLAG));
options.no_self_checking());
/* Instantiate an integer to count the number of error
* and determine if the simulation succeed or failed
*/
print_verilog_comment(fp, std::string("----- Error counter -------"));
fp << "\tinteger " << ERROR_COUNTER << "= 0;" << std::endl;
/* Add an empty line as splitter */
fp << std::endl;
if (!options.no_self_checking()) {
print_verilog_comment(fp, std::string("----- Error counter -------"));
fp << "\tinteger " << ERROR_COUNTER << "= 0;" << std::endl;
/* Add an empty line as splitter */
fp << std::endl;
}
}
/********************************************************************
@ -109,9 +109,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
/* Validate the file stream */
valid_file_stream(fp);
/* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
/* Instanciate benchmark */
print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------"));
/* Do NOT use explicit port mapping here:
@ -133,12 +131,6 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
/* Add an empty line as splitter */
fp << std::endl;
/* Condition ends for the benchmark instanciation */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
/********************************************************************
@ -301,7 +293,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
/* Start of testbench */
print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation, options.default_net_type());
print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation, options);
/* Call defined top-level module */
print_verilog_random_testbench_fpga_instance(fp, circuit_name,
@ -309,9 +301,11 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
options.explicit_port_mapping());
/* Call defined benchmark */
print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name,
atom_ctx, netlist_annotation,
options.explicit_port_mapping());
if (!options.no_self_checking()) {
print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name,
atom_ctx, netlist_annotation,
options.explicit_port_mapping());
}
/* Find clock port to be used */
std::vector<BasicPort> clock_ports = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME));
@ -340,22 +334,23 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
pin_constraints,
clock_port_names,
std::string(CHECKFLAG_PORT_POSTFIX),
clock_ports);
clock_ports,
options.no_self_checking());
print_verilog_testbench_check(fp,
std::string(AUTOCHECKED_SIMULATION_FLAG),
std::string(FORMAL_TB_SIM_START_PORT_NAME),
std::string(BENCHMARK_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX),
std::string(CHECKFLAG_PORT_POSTFIX),
std::string(ERROR_COUNTER),
atom_ctx,
netlist_annotation,
clock_port_names,
std::string(DEFAULT_CLOCK_NAME));
if (!options.no_self_checking()) {
print_verilog_testbench_check(fp,
std::string(FORMAL_TB_SIM_START_PORT_NAME),
std::string(BENCHMARK_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX),
std::string(CHECKFLAG_PORT_POSTFIX),
std::string(ERROR_COUNTER),
atom_ctx,
netlist_annotation,
clock_port_names,
std::string(DEFAULT_CLOCK_NAME));
}
float simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME,
simulation_parameters.num_clock_cycles(),
float simulation_time = find_operating_phase_simulation_time(simulation_parameters.num_clock_cycles(),
1./simulation_parameters.default_operating_clock_frequency(),
VERILOG_SIM_TIMESCALE);
@ -365,7 +360,8 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
std::string(circuit_name + std::string("_formal.vcd")),
std::string(FORMAL_TB_SIM_START_PORT_NAME),
std::string(ERROR_COUNTER),
simulation_time);
simulation_time,
options.no_self_checking());
/* Testbench ends*/
print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX));

87
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -204,16 +204,18 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
* while uses 'force' syntax to impost the bitstream at mem_inv port
*******************************************************************/
static
void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp,
const ModuleManager &module_manager,
const ModuleId &top_module,
const BitstreamManager &bitstream_manager,
const bool& output_datab_bits) {
void print_verilog_preconfig_top_module_force_bitstream(std::fstream &fp,
const ModuleManager &module_manager,
const ModuleId &top_module,
const BitstreamManager &bitstream_manager,
const bool& output_datab_bits) {
/* Validate the file stream */
valid_file_stream(fp);
print_verilog_comment(fp, std::string("----- Begin assign bitstream to configuration memories -----"));
fp << "initial begin" << std::endl;
for (const ConfigBlockId &config_block_id : bitstream_manager.blocks()) {
/* We only cares blocks with configuration bits */
if (0 == bitstream_manager.block_bits(config_block_id).size()) {
@ -242,31 +244,9 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp,
for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) {
config_data_values.push_back(bitstream_manager.bit_value(config_bit));
}
print_verilog_wire_constant_values(fp, config_data_port, config_data_values);
}
if (true == output_datab_bits) {
fp << "initial begin" << std::endl;
for (const ConfigBlockId &config_block_id : bitstream_manager.blocks()) {
/* We only cares blocks with configuration bits */
if (0 == bitstream_manager.block_bits(config_block_id).size()) {
continue;
}
/* Build the hierarchical path of the configuration bit in modules */
std::vector<ConfigBlockId> block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id);
/* Drop the first block, which is the top module, it should be replaced by the instance name here */
/* Ensure that this is the module we want to drop! */
VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0])));
block_hierarchy.erase(block_hierarchy.begin());
/* Build the full hierarchy path */
std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME);
for (const ConfigBlockId &temp_block : block_hierarchy) {
bit_hierarchy_path += std::string(".");
bit_hierarchy_path += bitstream_manager.block_name(temp_block);
}
bit_hierarchy_path += std::string(".");
print_verilog_force_wire_constant_values(fp, config_data_port, config_data_values);
if (true == output_datab_bits) {
/* Find the bit index in the parent block */
BasicPort config_datab_port(bit_hierarchy_path + generate_configurable_memory_inverted_data_out_name(),
bitstream_manager.block_bits(config_block_id).size());
@ -277,10 +257,10 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp,
}
print_verilog_force_wire_constant_values(fp, config_datab_port, config_datab_values);
}
fp << "end" << std::endl;
}
fp << "end" << std::endl;
print_verilog_comment(fp, std::string("----- End assign bitstream to configuration memories -----"));
}
@ -364,7 +344,8 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
const ModuleId &top_module,
const CircuitLibrary& circuit_lib,
const CircuitModelId& mem_model,
const BitstreamManager &bitstream_manager) {
const BitstreamManager &bitstream_manager,
const e_embedded_bitstream_hdl_type& embedded_bitstream_hdl_type) {
/* Skip the datab port if there is only 1 output port in memory model
* Currently, it assumes that the data output port is always defined while datab is optional
@ -379,21 +360,17 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----"));
print_verilog_preprocessing_flag(fp, std::string(ICARUS_SIMULATOR_FLAG));
/* Use assign syntax for Icarus simulator */
print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module,
bitstream_manager,
output_datab_bits);
fp << "`else" << std::endl;
/* Use assign syntax for Icarus simulator */
print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module,
if (EMBEDDED_BITSTREAM_HDL_IVERILOG == embedded_bitstream_hdl_type) {
print_verilog_preconfig_top_module_force_bitstream(fp, module_manager, top_module,
bitstream_manager,
output_datab_bits);
print_verilog_endif(fp);
/* Use deposit syntax for other simulators */
} else if (EMBEDDED_BITSTREAM_HDL_MODELSIM == embedded_bitstream_hdl_type) {
print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module,
bitstream_manager,
output_datab_bits);
}
print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----"));
}
@ -502,17 +479,23 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
CircuitModelId sram_model = config_protocol.memory_model();
VTR_ASSERT(true == circuit_lib.valid_model_id(sram_model));
/* Assign FPGA internal SRAM/Memory ports to bitstream values */
/* Assign FPGA internal SRAM/Memory ports to bitstream values, only output when needed */
print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module,
circuit_lib, sram_model,
bitstream_manager);
bitstream_manager,
options.embedded_bitstream_hdl_type());
/* Add signal initialization */
print_verilog_testbench_signal_initialization(fp,
std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME),
circuit_lib,
module_manager,
top_module);
/* Add signal initialization:
* Bypass writing codes to files due to the autogenerated codes are very large.
*/
if (true == options.include_signal_init()) {
print_verilog_testbench_signal_initialization(fp,
std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME),
circuit_lib,
module_manager,
top_module,
false);
}
/* Testbench ends*/
print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX));

39
openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp
View File

@ -13,6 +13,7 @@
#include "vtr_time.h"
/* Headers from openfpgautil library */
#include "openfpga_scale.h"
#include "openfpga_digest.h"
#include "openfpga_reserved_words.h"
@ -31,6 +32,7 @@ namespace openfpga {
* information, in order to interface different Verilog simulators
********************************************************************/
void print_verilog_simulation_info(const std::string& ini_fname,
const VerilogTestbenchOption& options,
const std::string& circuit_name,
const std::string& src_dir,
const AtomContext& atom_ctx,
@ -57,24 +59,39 @@ void print_verilog_simulation_info(const std::string& ini_fname,
VTR_ASSERT(true != ini_fname.empty());
mINI::INIStructure ini;
// std::map<char, int> units_map;
// units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6;
// units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15;
/* Compute simulation time period */
float simulation_time_period = find_simulation_time_period(1E-3,
num_program_clock_cycles,
1. / prog_clock_freq,
num_operating_clock_cycles,
1. / op_clock_freq);
/* Compute simulation time period: full testbench and pre-configured testbench has different length
* Currently, we only support the two types. And one of them must be enabled when outputting this file
*/
float simulation_time_period = 0.;
if (options.print_top_testbench()) {
simulation_time_period = find_simulation_time_period(options.time_unit(),
num_program_clock_cycles,
1. / prog_clock_freq,
num_operating_clock_cycles,
1. / op_clock_freq);
} else {
VTR_ASSERT(options.print_preconfig_top_testbench());
simulation_time_period = find_operating_phase_simulation_time(num_operating_clock_cycles,
1. / op_clock_freq,
options.time_unit());
}
/* Identify the testbench file name depending on the type */
std::string top_tb_name;
if (options.print_top_testbench()) {
top_tb_name = circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
} else {
VTR_ASSERT(options.print_preconfig_top_testbench());
top_tb_name = circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX);
}
/* Basic information */
ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject";
ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name;
ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX);
ini["SIMULATION_DECK"]["TOP_TB"] = top_tb_name;
ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period);
ini["SIMULATION_DECK"]["UNIT "] = "ms";
ini["SIMULATION_DECK"]["UNIT "] = unit_to_string(options.time_unit());
ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir);
ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME);
ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX));

2
openfpga/src/fpga_verilog/verilog_simulation_info_writer.h
View File

@ -9,6 +9,7 @@
#include "config_protocol.h"
#include "vpr_context.h"
#include "io_location_map.h"
#include "verilog_testbench_options.h"
/********************************************************************
* Function declaration
@ -18,6 +19,7 @@
namespace openfpga {
void print_verilog_simulation_info(const std::string& ini_fname,
const VerilogTestbenchOption& options,
const std::string& circuit_name,
const std::string& src_dir,
const AtomContext& atom_ctx,

40
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
View File

@ -21,9 +21,10 @@ VerilogTestbenchOption::VerilogTestbenchOption() {
print_top_testbench_ = false;
simulation_ini_path_.clear();
explicit_port_mapping_ = false;
support_icarus_simulator_ = false;
include_signal_init_ = false;
default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
time_unit_ = 1E-3;
verbose_output_ = false;
}
@ -74,14 +75,22 @@ bool VerilogTestbenchOption::include_signal_init() const {
return include_signal_init_;
}
bool VerilogTestbenchOption::support_icarus_simulator() const {
return support_icarus_simulator_;
bool VerilogTestbenchOption::no_self_checking() const {
return reference_benchmark_file_path_.empty();
}
e_verilog_default_net_type VerilogTestbenchOption::default_net_type() const {
return default_net_type_;
}
float VerilogTestbenchOption::time_unit() const {
return time_unit_;
}
e_embedded_bitstream_hdl_type VerilogTestbenchOption::embedded_bitstream_hdl_type() const {
return embedded_bitstream_hdl_type_;
}
bool VerilogTestbenchOption::verbose_output() const {
return verbose_output_;
}
@ -142,10 +151,6 @@ void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) {
include_signal_init_ = enabled;
}
void VerilogTestbenchOption::set_support_icarus_simulator(const bool& enabled) {
support_icarus_simulator_ = enabled;
}
void VerilogTestbenchOption::set_default_net_type(const std::string& default_net_type) {
/* Decode from net type string */;
if (default_net_type == std::string(VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_NONE])) {
@ -160,6 +165,27 @@ void VerilogTestbenchOption::set_default_net_type(const std::string& default_net
}
}
void VerilogTestbenchOption::set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type) {
/* Decode from HDL type string */;
if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES])) {
embedded_bitstream_hdl_type_ = NUM_EMBEDDED_BITSTREAM_HDL_TYPES;
} else if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG])) {
embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_IVERILOG;
} else if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM])) {
embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
} else {
VTR_LOG_WARN("Invalid embedded bitstream type: '%s'! Expect ['%s'|'%s'|'%s']\n",
embedded_bitstream_hdl_type.c_str(),
EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES],
EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG],
EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM]);
}
}
void VerilogTestbenchOption::set_time_unit(const float& time_unit) {
time_unit_ = time_unit;
}
void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
verbose_output_ = enabled;
}

19
openfpga/src/fpga_verilog/verilog_testbench_options.h
View File

@ -10,6 +10,15 @@
/* Begin namespace openfpga */
namespace openfpga {
/* Embedded bitstream code style */
enum e_embedded_bitstream_hdl_type {
EMBEDDED_BITSTREAM_HDL_IVERILOG,
EMBEDDED_BITSTREAM_HDL_MODELSIM,
NUM_EMBEDDED_BITSTREAM_HDL_TYPES
};
constexpr std::array<const char*, NUM_EMBEDDED_BITSTREAM_HDL_TYPES + 1> EMBEDDED_BITSTREAM_HDL_TYPE_STRING = {{"iverilog", "modelsim", "none"}}; //String versions of default net types
/********************************************************************
* Options for Verilog Testbench generator
* Typicall usage:
@ -34,8 +43,10 @@ class VerilogTestbenchOption {
std::string simulation_ini_path() const;
bool explicit_port_mapping() const;
bool include_signal_init() const;
bool support_icarus_simulator() const;
bool no_self_checking() const;
e_verilog_default_net_type default_net_type() const;
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const;
float time_unit() const;
bool verbose_output() const;
public: /* Public validator */
bool validate() const;
@ -59,8 +70,9 @@ class VerilogTestbenchOption {
void set_print_simulation_ini(const std::string& simulation_ini_path);
void set_explicit_port_mapping(const bool& enabled);
void set_include_signal_init(const bool& enabled);
void set_support_icarus_simulator(const bool& enabled);
void set_default_net_type(const std::string& default_net_type);
void set_time_unit(const float& time_unit);
void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type);
void set_verbose_output(const bool& enabled);
private: /* Internal Data */
std::string output_directory_;
@ -73,9 +85,10 @@ class VerilogTestbenchOption {
/* Print simulation ini is enabled only when the path is not empty */
std::string simulation_ini_path_;
bool explicit_port_mapping_;
bool support_icarus_simulator_;
bool include_signal_init_;
e_verilog_default_net_type default_net_type_;
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_;
float time_unit_;
bool verbose_output_;
};

126
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -304,7 +304,8 @@ void print_verilog_timeout_and_vcd(std::fstream& fp,
const std::string& vcd_fname,
const std::string& simulation_start_counter_name,
const std::string& error_counter_name,
const float& simulation_time) {
const float& simulation_time,
const bool& no_self_checking) {
/* Validate the file stream */
valid_file_stream(fp);
@ -323,16 +324,27 @@ void print_verilog_timeout_and_vcd(std::fstream& fp,
BasicPort sim_start_port(simulation_start_counter_name, 1);
fp << "initial begin" << std::endl;
fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << " <= 1'b1;" << std::endl;
if (!no_self_checking) {
fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << " <= 1'b1;" << std::endl;
}
fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl;
fp << "\t$display(\"Simulation start\");" << std::endl;
print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------"));
fp << "\t#" << std::setprecision(10) << simulation_time << std::endl;
fp << "\tif(" << error_counter_name << " == 0) begin" << std::endl;
fp << "\t\t$display(\"Simulation Succeed\");" << std::endl;
fp << "\tend else begin" << std::endl;
fp << "\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << error_counter_name << ");" << std::endl;
fp << "\tend" << std::endl;
if (!no_self_checking) {
fp << "\tif(" << error_counter_name << " == 0) begin" << std::endl;
fp << "\t\t$display(\"Simulation Succeed\");" << std::endl;
fp << "\tend else begin" << std::endl;
fp << "\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << error_counter_name << ");" << std::endl;
fp << "\tend" << std::endl;
} else {
VTR_ASSERT_SAFE(no_self_checking);
fp << "\t$display(\"Simulation Succeed\");" << std::endl;
}
fp << "\t$finish;" << std::endl;
fp << "end" << std::endl;
@ -366,7 +378,6 @@ std::vector<BasicPort> generate_verilog_testbench_clock_port(const std::vector<s
* Restriction: this function only supports single clock benchmarks!
*******************************************************************/
void print_verilog_testbench_check(std::fstream& fp,
const std::string& autochecked_preprocessing_flag,
const std::string& simulation_start_counter_name,
const std::string& benchmark_port_postfix,
const std::string& fpga_port_postfix,
@ -380,9 +391,7 @@ void print_verilog_testbench_check(std::fstream& fp,
/* Validate the file stream */
valid_file_stream(fp);
/* Add output autocheck conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, autochecked_preprocessing_flag);
/* Add output autocheck */
print_verilog_comment(fp, std::string("----- Begin checking output vectors -------"));
std::vector<BasicPort> clock_ports = generate_verilog_testbench_clock_port(clock_port_names, default_clock_name);
@ -460,9 +469,6 @@ void print_verilog_testbench_check(std::fstream& fp,
fp << std::endl;
}
/* Condition ends */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
@ -536,7 +542,8 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
const PinConstraints& pin_constraints,
const std::vector<std::string>& clock_port_names,
const std::string& check_flag_port_postfix,
const std::vector<BasicPort>& clock_ports) {
const std::vector<BasicPort>& clock_ports,
const bool& no_self_checking) {
/* Validate the file stream */
valid_file_stream(fp);
@ -575,25 +582,27 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
}
}
/* Add an empty line as splitter */
fp << std::endl;
/* Set 0 to registers for checking flags */
for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
/* Bypass non-I/O atom blocks ! */
if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) {
continue;
if (!no_self_checking) {
/* Add an empty line as splitter */
fp << std::endl;
for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
/* Bypass non-I/O atom blocks ! */
if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) {
continue;
}
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
/* Each logical block assumes a single-width port */
BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1);
fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl;
}
/* The block may be renamed as it contains special characters which violate Verilog syntax */
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
/* Each logical block assumes a single-width port */
BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1);
fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl;
}
fp << "\tend" << std::endl;
@ -664,7 +673,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
const std::string& benchmark_output_port_postfix,
const std::string& fpga_output_port_postfix,
const std::string& check_flag_port_postfix,
const std::string& autocheck_preprocessing_flag) {
const bool& no_self_checking) {
/* Validate the file stream */
valid_file_stream(fp);
@ -718,11 +727,9 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
/* Add an empty line as splitter */
fp << std::endl;
/* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, std::string(autocheck_preprocessing_flag));
/* Add an empty line as splitter */
fp << std::endl;
if (no_self_checking) {
return;
}
/* Instantiate wire for benchmark output */
print_verilog_comment(fp, std::string("----- Benchmark outputs -------"));
@ -767,12 +774,6 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
/* Add an empty line as splitter */
fp << std::endl;
/* Condition ends for the benchmark instanciation */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
/********************************************************************
@ -791,7 +792,8 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
const std::vector<CircuitPortId>& circuit_input_ports,
const ModuleManager& module_manager,
const ModuleId& parent_module,
const ModuleId& primitive_module) {
const ModuleId& primitive_module,
const bool& deposit_random_values) {
/* Validate the file stream */
valid_file_stream(fp);
@ -819,7 +821,8 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
child_hie_path,
circuit_lib, circuit_model, circuit_input_ports,
module_manager, child_module,
primitive_module);
primitive_module,
deposit_random_values);
} else {
/* If the child module is the primitive module,
* we output the signal initialization codes for the input ports
@ -828,7 +831,6 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
print_verilog_comment(fp, std::string("------ BEGIN driver initialization -----"));
fp << "\tinitial begin" << std::endl;
fp << "\t`ifdef " << VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG << std::endl;
for (const auto& input_port : circuit_input_ports) {
/* Only for formal verification: deposite a zero signal values */
@ -838,22 +840,17 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
fp << "\t\t$deposit(";
fp << child_hie_path << ".";
fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info, false);
fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0');
fp << ");" << std::endl;
}
fp << "\t`else" << std::endl;
if (!deposit_random_values) {
/* Regular case: deposite initial signal values: a random value */
for (const auto& input_port : circuit_input_ports) {
BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port));
input_port_info.set_origin_port_width(input_port_info.get_width());
fp << "\t\t$deposit(";
fp << child_hie_path << ".";
fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info, false);
fp << ", $random % 2 ? 1'b1 : 1'b0);" << std::endl;
fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0');
fp << ");" << std::endl;
} else {
VTR_ASSERT_SAFE(deposit_random_values);
fp << ", $random % 2 ? 1'b1 : 1'b0);" << std::endl;
}
}
fp << "\t`endif\n" << std::endl;
fp << "\tend" << std::endl;
print_verilog_comment(fp, std::string("------ END driver initialization -----"));
}
@ -871,7 +868,8 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
const std::string& top_instance_name,
const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager,
const ModuleId& top_module) {
const ModuleId& top_module,
const bool& deposit_random_values) {
/* Validate the file stream */
valid_file_stream(fp);
@ -911,7 +909,6 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
/* Add signal initialization Verilog codes */
fp << std::endl;
fp << "`ifdef " << VERILOG_SIGNAL_INIT_PREPROC_FLAG << std::endl;
for (const CircuitModelId& signal_init_circuit_model : signal_init_circuit_models) {
/* Find the module id corresponding to the circuit model from module graph */
ModuleId primitive_module = module_manager.find_module(circuit_lib.model_name(signal_init_circuit_model));
@ -922,10 +919,9 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
top_instance_name,
circuit_lib, signal_init_circuit_model, signal_init_circuit_ports.at(signal_init_circuit_model),
module_manager, top_module,
primitive_module);
primitive_module,
deposit_random_values);
}
fp << "`endif" << std::endl;
}
} /* end namespace openfpga */

12
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -56,13 +56,13 @@ void print_verilog_timeout_and_vcd(std::fstream& fp,
const std::string& vcd_fname,
const std::string& simulation_start_counter_name,
const std::string& error_counter_name,
const float& simulation_time);
const float& simulation_time,
const bool& no_self_checking);
std::vector<BasicPort> generate_verilog_testbench_clock_port(const std::vector<std::string>& clock_port_names,
const std::string& default_clock_name);
void print_verilog_testbench_check(std::fstream& fp,
const std::string& autochecked_preprocessing_flag,
const std::string& simulation_start_counter_name,
const std::string& benchmark_port_postfix,
const std::string& fpga_port_postfix,
@ -86,7 +86,8 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
const PinConstraints& pin_constraints,
const std::vector<std::string>& clock_port_names,
const std::string& check_flag_port_postfix,
const std::vector<BasicPort>& clock_ports);
const std::vector<BasicPort>& clock_ports,
const bool& no_self_checking);
void print_verilog_testbench_shared_ports(std::fstream& fp,
const AtomContext& atom_ctx,
@ -95,13 +96,14 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
const std::string& benchmark_output_port_postfix,
const std::string& fpga_output_port_postfix,
const std::string& check_flag_port_postfix,
const std::string& autocheck_preprocessing_flag);
const bool& no_self_checking);
void print_verilog_testbench_signal_initialization(std::fstream& fp,
const std::string& top_instance_name,
const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager,
const ModuleId& top_module);
const ModuleId& top_module,
const bool& deposit_random_values);
} /* end namespace openfpga */

86
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -702,12 +702,12 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
const SimulationSetting& simulation_parameters,
const ConfigProtocol& config_protocol,
const std::string& circuit_name,
const e_verilog_default_net_type& default_net_type) {
const VerilogTestbenchOption& options) {
/* Validate the file stream */
valid_file_stream(fp);
print_verilog_default_net_type_declaration(fp,
default_net_type);
options.default_net_type());
/* Print module definition */
fp << "module " << circuit_name << std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX);
@ -808,13 +808,15 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::string(AUTOCHECKED_SIMULATION_FLAG));
options.no_self_checking());
/* Instantiate an integer to count the number of error and
* determine if the simulation succeed or failed
*/
print_verilog_comment(fp, std::string("----- Error counter: Deposit an error for config_done signal is not raised at the beginning -----"));
fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 1;" << std::endl;
if (!options.no_self_checking()) {
print_verilog_comment(fp, std::string("----- Error counter: Deposit an error for config_done signal is not raised at the beginning -----"));
fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 1;" << std::endl;
}
}
/********************************************************************
@ -914,9 +916,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
/* Validate the file stream */
valid_file_stream(fp);
/* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
/* Instanciate benchmark */
print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------"));
/* Do NOT use explicit port mapping here:
@ -938,12 +938,6 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
/* Add an empty line as splitter */
fp << std::endl;
/* Condition ends for the benchmark instanciation */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
/********************************************************************
@ -1811,16 +1805,12 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp,
*******************************************************************/
static
void print_verilog_top_testbench_check(std::fstream& fp,
const std::string& autochecked_preprocessing_flag,
const std::string& config_done_port_name,
const std::string& error_counter_name) {
/* Validate the file stream */
valid_file_stream(fp);
/* Add output autocheck conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, autochecked_preprocessing_flag);
print_verilog_comment(fp, std::string("----- Configuration done must be raised in the end -------"));
BasicPort config_done_port(config_done_port_name, 1);
@ -1834,9 +1824,6 @@ void print_verilog_top_testbench_check(std::fstream& fp,
write_tab_to_file(fp, 1);
fp << "end" << std::endl;
/* Condition ends */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
@ -1925,7 +1912,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
pin_constraints,
simulation_parameters, config_protocol,
circuit_name,
options.default_net_type());
options);
/* Find the clock period */
float prog_clock_period = (1./simulation_parameters.programming_clock_frequency());
@ -2006,11 +1993,13 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
/* Instanciate input benchmark */
print_verilog_top_testbench_benchmark_instance(fp,
circuit_name,
atom_ctx,
netlist_annotation,
explicit_port_mapping);
if (!options.no_self_checking()) {
print_verilog_top_testbench_benchmark_instance(fp,
circuit_name,
atom_ctx,
netlist_annotation,
explicit_port_mapping);
}
/* load bitstream to FPGA fabric in a configuration phase */
print_verilog_full_testbench_bitstream(fp,
@ -2029,7 +2018,8 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME),
circuit_lib,
module_manager,
top_module);
top_module,
true);
}
@ -2048,26 +2038,27 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
pin_constraints,
clock_port_names,
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::vector<BasicPort>(1, BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1)));
std::vector<BasicPort>(1, BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1)),
options.no_self_checking());
/* Add output autocheck */
print_verilog_testbench_check(fp,
std::string(AUTOCHECKED_SIMULATION_FLAG),
std::string(TOP_TESTBENCH_SIM_START_PORT_NAME),
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::string(TOP_TESTBENCH_ERROR_COUNTER),
atom_ctx,
netlist_annotation,
clock_port_names,
std::string(TOP_TB_OP_CLOCK_PORT_NAME));
if (!options.no_self_checking()) {
/* Add output autocheck */
print_verilog_testbench_check(fp,
std::string(TOP_TESTBENCH_SIM_START_PORT_NAME),
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::string(TOP_TESTBENCH_ERROR_COUNTER),
atom_ctx,
netlist_annotation,
clock_port_names,
std::string(TOP_TB_OP_CLOCK_PORT_NAME));
/* Add autocheck for configuration phase */
print_verilog_top_testbench_check(fp,
std::string(AUTOCHECKED_SIMULATION_FLAG),
std::string(TOP_TB_CONFIG_DONE_PORT_NAME),
std::string(TOP_TESTBENCH_ERROR_COUNTER));
/* Add autocheck for configuration phase */
print_verilog_top_testbench_check(fp,
std::string(TOP_TB_CONFIG_DONE_PORT_NAME),
std::string(TOP_TESTBENCH_ERROR_COUNTER));
}
/* Find simulation time */
float simulation_time = find_simulation_time_period(VERILOG_SIM_TIMESCALE,
@ -2085,7 +2076,8 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
std::string(circuit_name + std::string("_formal.vcd")),
std::string(TOP_TESTBENCH_SIM_START_PORT_NAME),
std::string(TOP_TESTBENCH_ERROR_COUNTER),
std::ceil(simulation_time));
std::ceil(simulation_time),
options.no_self_checking());
/* Testbench ends*/

5
openfpga/src/utils/simulation_utils.cpp
View File

@ -14,14 +14,13 @@ namespace openfpga {
/********************************************************************
* Compute the time period for the simulation
*******************************************************************/
float find_operating_phase_simulation_time(const int& factor,
const int& num_op_clock_cycles,
float find_operating_phase_simulation_time(const int& num_op_clock_cycles,
const float& op_clock_period,
const float& timescale) {
/* Take into account the prog_reset and reset cycles
* 1e9 is to change the unit to ns rather than second
*/
return ((float)factor * (float)num_op_clock_cycles * op_clock_period) / timescale;
return ((float)num_op_clock_cycles * op_clock_period) / timescale;
}
/********************************************************************

3
openfpga/src/utils/simulation_utils.h
View File

@ -12,8 +12,7 @@
/* begin namespace openfpga */
namespace openfpga {
float find_operating_phase_simulation_time(const int& factor,
const int& num_op_clock_cycles,
float find_operating_phase_simulation_time(const int& num_op_clock_cycles,
const float& op_clock_period,
const float& timescale);

21
openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v Normal file
View File

@ -0,0 +1,21 @@
// Creating a scaleable adder
module adder_16(cout, sum, a, b, cin);
parameter size = 6; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule

21
openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v Normal file
View File

@ -0,0 +1,21 @@
// Creating a scaleable adder
module adder_4(cout, sum, a, b, cin);
parameter size = 4; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule

21
openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v Normal file
View File

@ -0,0 +1,21 @@
// Creating a scaleable adder
module adder_6(cout, sum, a, b, cin);
parameter size = 6; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule

0
openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act → openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.act
View File

0
openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif → openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.eblif
View File

0
openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v → openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v
View File

0
openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v → openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_out.v
View File

94
openfpga_flow/openfpga_cell_library/verilog/dff.v
View File

@ -20,12 +20,7 @@ always @ (posedge CK) begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
`else
assign Q = 1'bZ;
`endif
assign Q = q_reg;
endmodule //End Of Module
@ -46,14 +41,8 @@ always @ (posedge CK) begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module
@ -79,12 +68,7 @@ end else begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
`else
assign Q = 1'bZ;
`endif
assign Q = q_reg;
endmodule //End Of Module
@ -111,14 +95,8 @@ end else begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module
@ -144,14 +122,8 @@ end else begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module
@ -178,14 +150,8 @@ end else begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module
@ -211,14 +177,8 @@ end else begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module
@ -249,14 +209,8 @@ end else begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module
@ -349,14 +303,8 @@ end else begin
q_reg <= D;
end
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign QN = !Q;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = !Q;
endmodule //End Of Module
@ -462,13 +410,7 @@ end
assign CFGQ = CFGE ? Q : 1'b0;
assign CFGQN = CFGE ? QN : 1'b1;
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign QN = !Q;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = !Q;
endmodule //End Of Module

4
openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga
View File

@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
# Finish and exit OpenFPGA
exit

4
openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
View File

@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga
View File

@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga
View File

@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga
View File

@ -59,8 +59,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga
View File

@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

74
openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga Normal file
View File

@ -0,0 +1,74 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

2
openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga
View File

@ -59,8 +59,6 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
# Write the SDC files for PnR backend
# - Turn on every options here

2
openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga
View File

@ -59,8 +59,6 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
# Write the SDC files for PnR backend
# - Turn on every options here

2
openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga
View File

@ -52,8 +52,6 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --support_icarus_simulator
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis

5
openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga
View File

@ -57,9 +57,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Write the SDC files for PnR backend
# - Turn on every options here

76
openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga Normal file
View File

@ -0,0 +1,76 @@
# Run VPR for the 'and' design
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
# This is due to the Fc_in of clock port is set to 0 for global wiring
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

5
openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga
View File

@ -61,9 +61,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga
View File

@ -54,8 +54,8 @@ write_fabric_verilog --file ./SRC \
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Finish and exit OpenFPGA
exit

57
openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga Normal file
View File

@ -0,0 +1,57 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --embed_bitstream ${OPENFPGA_EMBEDDED_BITSTREAM_HDL_TYPE} --file ./SRC --explicit_port_mapping
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

75
openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga Normal file
View File

@ -0,0 +1,75 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

12
openfpga_flow/openfpga_shell_scripts/rename_scripts.sh
View File

@ -1,4 +1,12 @@
foreach i (*.openfpga)
sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i
sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i
# sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i
# sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i
end
foreach i (*.openfpga)
sed -i 's/--support_icarus_simulator//g' $i
end
foreach i (*.openfpga)
sed -i 's/write_preconfigured_fabric_wrapper/write_preconfigured_fabric_wrapper --embed_bitstream iverilog/g' $i
end

4
openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/regression_test_scripts/basic_reg_test.sh
View File

@ -53,6 +53,10 @@ run-task basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread
run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs
run-task basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
echo -e "Testing testbenches without self checking features";
run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs
run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking --debug --show_thread_logs
echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
run-task basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
run-task basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs

4
openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
View File

@ -136,3 +136,7 @@ run-task fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
echo -e "Testing through channels in tileable routing";
run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
echo -e "Testing the generation of preconfigured fabric wrapper for different HDL simulators";
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none --debug --show_thread_logs
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug --show_thread_logs

10
openfpga_flow/scripts/run_fpga_flow.py
View File

@ -741,11 +741,6 @@ def run_netlists_verification(exit_if_fail=True):
command = [cad_tools["iverilog_path"]]
command += ["-o", compiled_file]
fpga_define_file = "./SRC/define_simulation.v"
fpga_define_file_bk = "./SRC/define_simulation.v.bak"
shutil.copy(fpga_define_file, fpga_define_file_bk)
with open(fpga_define_file, "r") as fp:
fpga_defines = fp.readlines()
command += ["./SRC/%s_include_netlists.v" % args.top_module]
command += ["-s"]
@ -753,11 +748,6 @@ def run_netlists_verification(exit_if_fail=True):
command += [tb_top_formal]
else:
command += [tb_top_autochecked]
with open(fpga_define_file, "w") as fp:
for eachLine in fpga_defines:
if not (("ENABLE_FORMAL_VERIFICATION" in eachLine) or
"FORMAL_SIMULATION" in eachLine):
fp.write(eachLine)
run_command("iverilog_verification", "iverilog_output.txt", command)
vvp_command = ["vvp", compiled_file]

1
openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf
View File

@ -34,4 +34,3 @@ bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf
View File

@ -36,4 +36,3 @@ bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=

5
openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf
View File

@ -16,9 +16,11 @@ timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_device_layout=
openfpga_fast_configuration=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
@ -34,4 +36,3 @@ bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=

36
openfpga_flow/tasks/basic_tests/full_testbench/full_testbench_without_self_checking/config/task.conf Normal file
View File

@ -0,0 +1,36 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=
openfpga_fast_configuration=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench0_top = and2_latch
bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=

3
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf
View File

@ -16,9 +16,10 @@ timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=auto
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml

35
openfpga_flow/tasks/basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking/config/task.conf Normal file
View File

@ -0,0 +1,35 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench0_top = and2_latch
bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

2
openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf
View File

@ -16,7 +16,7 @@ timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2

35
openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim/config/task.conf Normal file
View File

@ -0,0 +1,35 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_embedded_bitstream_hdl_type=modelsim
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
[SYNTHESIS_PARAM]
bench0_top = and2
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

35
openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_none/config/task.conf Normal file
View File

@ -0,0 +1,35 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_embedded_bitstream_hdl_type=none
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
[SYNTHESIS_PARAM]
bench0_top = and2
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

14
openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
View File

@ -27,18 +27,20 @@ yosys_args = -family qlf_k4n8 -no_ff_map
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
[SYNTHESIS_PARAM]
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench1_top = adder_8
bench0_top = adder_4
bench1_top = adder_6
bench2_top = adder_8
bench3_top = adder_16
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
##########################
# The output verilog of yosys is not synthesizable!!!
# Turn off verification for now
# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=