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[Test] Patch regression tests for fpga bitstream

This commit is contained in:
tangxifan 2021-04-19 17:15:14 -06:00
parent 9b3dcc65bd
commit 2fa370d7d5
1 changed files with 1 additions and 1 deletions
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openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh
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@ -24,4 +24,4 @@ echo -e "Testing repacker capability in identifying wire LUTs";
run-task fpga_bitstream/repack_wire_lut --debug --show_thread_logs
echo -e "Testing overloading default paths for programmable interconnect when generating bitstream";
run-task fpga_bitstream/overload_mux_default_path--debug --show_thread_logs
run-task fpga_bitstream/overload_mux_default_path --debug --show_thread_logs