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[Doc] Add new bitstream setting syntex 'interconnect' to documentation

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tangxifan 2021-04-19 16:37:21 -06:00
parent 17fb532ffa
commit 9b3dcc65bd
1 changed files with 40 additions and 4 deletions
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44
docs/source/manual/file_formats/bitstream_setting.rst
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@ -6,19 +6,35 @@ Bitstream Setting (.xml)
An example of bitstream settings is shown as follows.
This can define a hard-coded bitstream for a reconfigurable resource in FPGA fabrics.
.. warning:: Bitstream setting is a feature for power-users. It may cause wrong bitstream to be generated. For example, the hard-coded bitstream is not compatible with LUTs whose nets may be swapped during routing stage (cause a change on the truth table as well as bitstream). It is users's responsibility to ensure correct bitstream.
.. code-block:: xml
<openfpga_bitstream_setting>
<pb_type name="<string>" source="eblif" content=".param LUT" is_mode_select_bistream="true" bitstream_offset="1"/>
<interconnect name="<string>" default_path="<string>"/>
</openfpga_bitstream_setting>
.. option:: pb_type="<string>"
pb_type-related Settings
^^^^^^^^^^^^^^^^^^^^^^^^
The ``pb_type`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example, ``pb_type="clb.fle[arithmetic].soft_adder.adder_lut4"``
The following syntax are applicable to the XML definition tagged by ``pb_type`` in bitstream setting files.
.. option:: name="<string>"
The ``pb_type`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example,
.. code-block:: xml
pb_type="clb.fle[arithmetic].soft_adder.adder_lut4"
.. option:: source="<string>"
The source of the ``pb_type`` bitstream, which could be from a ``.eblif`` file. For example, ``source="eblif"``.
The source of the ``pb_type`` bitstream, which could be from a ``.eblif`` file. For example,
.. code-block:: xml
source="eblif"
.. option:: content="<string>"
@ -33,5 +49,25 @@ This can define a hard-coded bitstream for a reconfigurable resource in FPGA fab
Specify the offset to be applied when overloading the bitstream to a target. For example, a LUT may have a 16-bit bitstream. When ``offset=1``, bitstream overloading will skip the first bit and start from the second bit of the 16-bit bitstream.
.. warning:: Bitstream setting is a feature for power-users. It may cause wrong bitstream to be generated. For example, the hard-coded bitstream is not compatible with LUTs whose nets may be swapped during routing stage (cause a change on the truth table as well as bitstream). It is users's responsibility to ensure correct bitstream.
Interconnection-related Settings
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The following syntax are applicable to the XML definition tagged by ``interconnect`` in bitstream setting files.
.. option:: name="<string>"
The ``interconnect`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example,
.. code-block:: xml
pb_type="clb.fle[arithmetic].mux1"
.. option:: default_path="<string>"
The default path denotes an input name that is consistent with VPR's architecture description. For example, in VPR architecture, there is a mux defined as
.. code-block:: xml
<mux name="mux1" input="iopad.inpad ff.Q" output="io.inpad"/>
The default path can be either ``iopad.inpad`` or ``ff.Q`` which corresponds to the first input and the second input respectively.