[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF

2021-10-30 14:47:37 -07:00 · 2021-10-30 14:47:37 -07:00 · b7ad61227d
parent ec184ef532
commit b7ad61227d
1 changed files with 19 additions and 1 deletions
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
@ -8,7 +8,25 @@ proc
 techmap -D NO_LUT -map +/adff2dff.v

 # Synthesis
-synth -top ${TOP_MODULE} -flatten
+opt_expr
+opt_clean
+check
+opt -nodffe -nosdff
+fsm
+opt -nodffe -nosdff
+wreduce
+peepopt
+opt_clean
+opt -nodffe -nosdff
+memory -nomap
+opt_clean
+opt -fast -full -nodffe -nosdff
+memory_map
+opt -full -nodffe -nosdff
+techmap
+opt -fast -nodffe -nosdff
+clean
+
 clean

 # LUT mapping