From b7ad61227de9be1d9bbd52c48a9c9677bc6fecc1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 Oct 2021 14:47:37 -0700
Subject: [PATCH] [Flow] Flatten the synthesis recipe in default yosys script
 to disable the mapping on DFFE and SDFF

---
 .../ys_tmpl_yosys_vpr_flow_with_rewrite.ys    | 20 ++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
index edcce4c23..f614760dc 100644
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
@@ -8,7 +8,25 @@ proc
 techmap -D NO_LUT -map +/adff2dff.v
 
 # Synthesis
-synth -top ${TOP_MODULE} -flatten
+opt_expr
+opt_clean
+check
+opt -nodffe -nosdff
+fsm
+opt -nodffe -nosdff
+wreduce
+peepopt
+opt_clean
+opt -nodffe -nosdff
+memory -nomap
+opt_clean
+opt -fast -full -nodffe -nosdff
+memory_map
+opt -full -nodffe -nosdff
+techmap
+opt -fast -nodffe -nosdff
+clean
+
 clean
 
 # LUT mapping