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This commit is contained in:
ANDREW HARRIS POND 2021-07-01 15:28:59 -06:00
parent db9231c225
commit 2567fbee05
5 changed files with 34 additions and 20 deletions
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13
openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
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@ -19,6 +19,9 @@
//
//////////////////////////////////////////////////////////////////////////////////
// Uncomment if using Vivado to synthesize the design. This will enable the initial block
// If using Yosys, initial blocks are not supported, and cannot be included.
// `define VIVADO_SYNTHESIS
module clock_divider (
input clk_in,
@ -29,10 +32,12 @@ module clock_divider (
reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter;
// initial begin
// clkdiv_counter <= 0;
// clk_out <= 0;
// end
`ifdef VIVADO_SYNTHESIS
initial begin
clkdiv_counter <= 0;
clk_out <= 0;
end
`endif
// Divide pl_clk (50MHz) to 1MHz
always @(posedge clk_in) begin

22
openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
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@ -19,6 +19,10 @@
//
//////////////////////////////////////////////////////////////////////////////////
// Uncomment if using Vivado to synthesize the design. This will enable the initial block
// If using Yosys, initial blocks are not supported, and cannot be included.
// `define VIVADO_SYNTHESIS
module pulse_generator(
input clk_in,
input repeated, // Specify if the pulse should be generated repeatedly
@ -35,14 +39,16 @@ module pulse_generator(
reg [PULSE_COUNTER_SIZE - 1 : 0] pulse_width_counter;
reg pulse_start;
reg pulse_end;
// initial begin
// pulse <= INITIAL_VALUE;
// pulse_start <= 1'b0;
// pulse_end <= 1'b0;
// wait_cycle_counter <= 0;
// pulse_width_counter <= 0;
// end
`ifdef VIVADO_SYNTHESIS
initial begin
pulse <= INITIAL_VALUE;
pulse_start <= 1'b0;
pulse_end <= 1'b0;
wait_cycle_counter <= 0;
pulse_width_counter <= 0;
end
`endif
// Wait a number of clock cycles, hold the initial value
always @(posedge clk_in) begin

5
openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
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@ -19,6 +19,9 @@
//
//////////////////////////////////////////////////////////////////////////////////
// Uncomment if using Vivado to synthesize the design. This will enable the initial block
// If using Yosys, initial blocks are not supported, and cannot be included.
// `define VIVADO_SYNTHESIS
module reset_generator(
input clk,
@ -30,10 +33,12 @@ module reset_generator(
reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter;
`ifdef VIVADO_SYNTHESIS
initial begin
pulse <= INITIAL_VALUE;
active_cycle_counter <= 0;
end
`endif
// Wait a number of clock cycles, hold the initial value
always @(posedge clk) begin

8
openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh
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@ -7,15 +7,13 @@ PYTHON_EXEC=python3.8
# OpenFPGA Shell with VPR8
##############################################
echo -e "Micro benchmark regression tests";
# run-task benchmark_sweep/counter --debug --show_thread_logs
# run-task benchmark_sweep/mac_units --debug --show_thread_logs
run-task benchmark_sweep/counter --debug --show_thread_logs
run-task benchmark_sweep/mac_units --debug --show_thread_logs
# Verify MCNC big20 benchmark suite with ModelSim
# Please make sure you have ModelSim installed in the environment
# Otherwise, it will fail
# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
# run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
run-task benchmark_sweep/signal_gen --debug --show_thread_logs

6
openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf
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@ -27,15 +27,15 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
[SYNTHESIS_PARAM]
bench0_top = clock_divider
bench0_chan_width = 300
bench1_top = pulse_generator
bench1_chan_width = 300
# bench1_top = pulse_generator
# bench1_chan_width = 300
# bench2_top = reset_generator
# bench2_chan_width = 300