From 2567fbee05ac26d2b6c1a015464f03267945c586 Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Thu, 1 Jul 2021 15:28:59 -0600 Subject: [PATCH] ready to merge --- .../signal_gen/clock_divider.v | 13 +++++++---- .../signal_gen/pulse_generator.v | 22 ++++++++++++------- .../signal_gen/reset_generator.v | 5 +++++ .../micro_benchmark_reg_test.sh | 8 +++---- .../signal_gen/config/task.conf | 6 ++--- 5 files changed, 34 insertions(+), 20 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v index 8172b7c6d..3cb3f9899 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v @@ -19,6 +19,9 @@ // ////////////////////////////////////////////////////////////////////////////////// +// Uncomment if using Vivado to synthesize the design. This will enable the initial block +// If using Yosys, initial blocks are not supported, and cannot be included. +// `define VIVADO_SYNTHESIS module clock_divider ( input clk_in, @@ -29,10 +32,12 @@ module clock_divider ( reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter; - // initial begin - // clkdiv_counter <= 0; - // clk_out <= 0; - // end +`ifdef VIVADO_SYNTHESIS + initial begin + clkdiv_counter <= 0; + clk_out <= 0; + end +`endif // Divide pl_clk (50MHz) to 1MHz always @(posedge clk_in) begin diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v index ff3391d55..1f092e6a0 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v @@ -19,6 +19,10 @@ // ////////////////////////////////////////////////////////////////////////////////// +// Uncomment if using Vivado to synthesize the design. This will enable the initial block +// If using Yosys, initial blocks are not supported, and cannot be included. +// `define VIVADO_SYNTHESIS + module pulse_generator( input clk_in, input repeated, // Specify if the pulse should be generated repeatedly @@ -35,14 +39,16 @@ module pulse_generator( reg [PULSE_COUNTER_SIZE - 1 : 0] pulse_width_counter; reg pulse_start; reg pulse_end; - - // initial begin - // pulse <= INITIAL_VALUE; - // pulse_start <= 1'b0; - // pulse_end <= 1'b0; - // wait_cycle_counter <= 0; - // pulse_width_counter <= 0; - // end + +`ifdef VIVADO_SYNTHESIS + initial begin + pulse <= INITIAL_VALUE; + pulse_start <= 1'b0; + pulse_end <= 1'b0; + wait_cycle_counter <= 0; + pulse_width_counter <= 0; + end +`endif // Wait a number of clock cycles, hold the initial value always @(posedge clk_in) begin diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v index f949e722a..6de4b6980 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v @@ -19,6 +19,9 @@ // ////////////////////////////////////////////////////////////////////////////////// +// Uncomment if using Vivado to synthesize the design. This will enable the initial block +// If using Yosys, initial blocks are not supported, and cannot be included. +// `define VIVADO_SYNTHESIS module reset_generator( input clk, @@ -30,10 +33,12 @@ module reset_generator( reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter; +`ifdef VIVADO_SYNTHESIS initial begin pulse <= INITIAL_VALUE; active_cycle_counter <= 0; end +`endif // Wait a number of clock cycles, hold the initial value always @(posedge clk) begin diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 44ecacd30..5f958e261 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -7,15 +7,13 @@ PYTHON_EXEC=python3.8 # OpenFPGA Shell with VPR8 ############################################## echo -e "Micro benchmark regression tests"; -# run-task benchmark_sweep/counter --debug --show_thread_logs -# run-task benchmark_sweep/mac_units --debug --show_thread_logs +run-task benchmark_sweep/counter --debug --show_thread_logs +run-task benchmark_sweep/mac_units --debug --show_thread_logs # Verify MCNC big20 benchmark suite with ModelSim # Please make sure you have ModelSim installed in the environment # Otherwise, it will fail -# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs +run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim - -# run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs run-task benchmark_sweep/signal_gen --debug --show_thread_logs diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index 6158af998..c6306d7da 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -27,15 +27,15 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v # bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v [SYNTHESIS_PARAM] bench0_top = clock_divider bench0_chan_width = 300 -bench1_top = pulse_generator -bench1_chan_width = 300 +# bench1_top = pulse_generator +# bench1_chan_width = 300 # bench2_top = reset_generator # bench2_chan_width = 300