[Script] Add dff with active-low async reset to default yosys tech lib

openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v

@@ -17,6 +17,16 @@ module \$_DFF_PP0_ (D, C, R, Q);
     dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
 endmodule
 
+// Async active-low reset
+module \$_DFF_PN0_ (D, C, R, Q);
+    input D;
+    input C;
+    input R;
+    output Q;
+    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+    dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
+endmodule
+
 // Async reset, enable
 module  \$_DFFE_PP0P_ (D, C, E, R, Q);
     input D;

openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v

@@ -76,6 +76,37 @@ module dffre(
         endcase
 endmodule
 
+//-----------------------------
+// D-type flip-flop with active-low asynchronous reset
+//-----------------------------
+(* abc9_flop, lib_whitebox *)
+module dffrn(
+    output reg Q,
+    input D,
+    input RN,
+    (* clkbuf_sink *)
+    (* invertible_pin = "IS_C_INVERTED" *)
+    input C
+);
+    parameter [0:0] INIT = 1'b0;
+    parameter [0:0] IS_C_INVERTED = 1'b0;
+    initial Q = INIT;
+    case(|IS_C_INVERTED)
+          1'b0:
+            always @(posedge C or negedge RN)
+                if (RN == 1'b0)
+                        Q <= 1'b0;
+                else
+                        Q <= D;
+          1'b1:
+            always @(negedge C or negedge RN)
+                if (RN == 1'b0)
+                        Q <= 1'b0;
+                else
+                        Q <= D;
+    endcase
+endmodule
+
 (* abc9_flop, lib_whitebox *)
 module latchre (
     output reg Q,