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[Script] Update openfpga shell script with fast configuration option

This commit is contained in:
tangxifan 2021-06-04 11:28:10 -06:00
parent 81048d3698
commit f5e90c9467
1 changed files with 1 additions and 1 deletions
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openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
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@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION}
# Write the SDC files for PnR backend
# - Turn on every options here