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[Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition

This commit is contained in:
tangxifan 2021-04-24 14:56:10 -06:00
parent 148da80869
commit a3a98fa21d
1 changed files with 3 additions and 3 deletions
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6
openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -210,9 +210,9 @@
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="A" lib_name="A" size="16"/>
<port type="input" prefix="B" lib_name="B" size="16"/>
<port type="output" prefix="Y" lib_name="Y" size="32"/>
<port type="input" prefix="A" lib_name="a" size="16"/>
<port type="input" prefix="B" lib_name="b" size="16"/>
<port type="output" prefix="Y" lib_name="out" size="32"/>
<port type="sram" prefix="mode" lib_name="mode" size="1" mode_select="true" circuit_model_name="DFFRQ" default_val="0"/>
</circuit_model>
</circuit_library>