[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks

openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act

@@ -1,22 +0,0 @@
-clk0 0.505000 0.204400
-rst0 0.491000 0.206000
-clk1 0.472000 0.204400
-rst1 0.501400 0.204600
-q1[0] 0.278800 0.557400
-q1[1] 0.240600 0.268800
-q1[2] 0.178200 0.120000
-q1[3] 0.098400 0.041600
-q0[0] 0.283400 0.566600
-q0[1] 0.246800 0.272000
-q0[2] 0.181000 0.122200
-q0[3] 0.093200 0.048800
-n34 0.178200 0.068356
-n38 0.098400 0.002698
-$abc$226$new_n22_ 0.880800 0.004943
-n42 0.283400 0.129291
-n46 0.246800 0.084119
-n50 0.181000 0.067113
-n54 0.093200 0.002644
-$abc$226$new_n27_ 0.883200 0.005398
-n26 0.278800 0.038636
-n30 0.240600 0.082416

openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif

@@ -1,48 +0,0 @@
-# Benchmark "counter4bit_2clock" written by ABC on Wed Jan 13 13:27:00 2021
-.model counter4bit_2clock
-.inputs clk0 rst0 clk1 rst1 
-.outputs q0[0] q0[1] q0[2] q0[3] q1[0] q1[1] \
-q1[2] q1[3] 
-
-.latch n26 q1[0] re clk1 2
-.latch n30 q1[1] re clk1 2
-.latch n34 q1[2] re clk1 2
-.latch n38 q1[3] re clk1 2
-.latch n42 q0[0] re clk0 2
-.latch n46 q0[1] re clk0 2
-.latch n50 q0[2] re clk0 2
-.latch n54 q0[3] re clk0 2
-
-.names q1[0] q1[1] rst1 q1[2] n34
--001 1
-0-01 1
-1100 1
-.names rst1 $abc$226$new_n22_ n38
-00 1
-.names q1[2] q1[0] q1[1] q1[3] $abc$226$new_n22_
---00 1
--0-0 1
-0--0 1
-1111 1
-.names rst0 q0[0] n42
-00 1
-.names rst0 q0[1] q0[0] n46
-001 1
-010 1
-.names q0[1] q0[0] rst0 q0[2] n50
--001 1
-0-01 1
-1100 1
-.names rst0 $abc$226$new_n27_ n54
-00 1
-.names q0[2] q0[1] q0[0] q0[3] $abc$226$new_n27_
---00 1
--0-0 1
-0--0 1
-1111 1
-.names q1[0] rst1 n26
-00 1
-.names rst1 q1[0] q1[1] n30
-001 1
-010 1
-.end

openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v

@@ -1,60 +0,0 @@
-/* Generated by Yosys 0.9+2406 (git sha1 a0606e09, gcc 8.4.0 -fPIC -Os) */
-
-module counter4bit_2clock(clk0, rst0, clk1, rst1, \q0[0] , \q0[1] , \q0[2] , \q0[3] , \q1[0] , \q1[1] , \q1[2] , \q1[3] );
-  wire _00_;
-  wire _01_;
-  input clk0;
-  input clk1;
-  wire n26;
-  wire n30;
-  wire n34;
-  wire n38;
-  wire n42;
-  wire n46;
-  wire n50;
-  wire n54;
-  output \q0[0] ;
-  reg \q0[0] ;
-  output \q0[1] ;
-  reg \q0[1] ;
-  output \q0[2] ;
-  reg \q0[2] ;
-  output \q0[3] ;
-  reg \q0[3] ;
-  output \q1[0] ;
-  reg \q1[0] ;
-  output \q1[1] ;
-  reg \q1[1] ;
-  output \q1[2] ;
-  reg \q1[2] ;
-  output \q1[3] ;
-  reg \q1[3] ;
-  input rst0;
-  input rst1;
-  always @(posedge clk1)
-      \q1[0]  <= n26;
-  always @(posedge clk1)
-      \q1[1]  <= n30;
-  always @(posedge clk1)
-      \q1[2]  <= n34;
-  always @(posedge clk1)
-      \q1[3]  <= n38;
-  always @(posedge clk1)
-      \q0[0]  <= n42;
-  always @(posedge clk1)
-      \q0[1]  <= n46;
-  always @(posedge clk1)
-      \q0[2]  <= n50;
-  always @(posedge clk1)
-      \q0[3]  <= n54;
-  assign n38 = 4'h1 >> { _00_, rst1 };
-  assign _00_ = 16'h807f >> { \q1[3] , \q1[1] , \q1[0] , \q1[2]  };
-  assign n42 = 4'h1 >> { \q0[0] , rst0 };
-  assign n46 = 8'h14 >> { \q0[0] , \q0[1] , rst0 };
-  assign n50 = 16'h0708 >> { \q0[2] , rst0, \q0[0] , \q0[1]  };
-  assign n54 = 4'h1 >> { _01_, rst0 };
-  assign _01_ = 16'h807f >> { \q0[3] , \q0[0] , \q0[1] , \q0[2]  };
-  assign n26 = 4'h1 >> { rst1, \q1[0]  };
-  assign n30 = 8'h14 >> { \q1[1] , \q1[0] , rst1 };
-  assign n34 = 16'h0708 >> { \q1[2] , rst1, \q1[1] , \q1[0]  };
-endmodule

openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v

@@ -1,4 +1,4 @@
-module counter4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
+module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
 
     input clk0;
     input rst0;

openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v

@@ -1,4 +1,4 @@
-module counter4bit_2clock_tb;
+module counter_4bit_2clock_tb;
 
 	reg clk0, rst0;
 	wire [3:0] q0;
@@ -6,12 +6,12 @@ module counter4bit_2clock_tb;
 	reg clk1, rst1;
 	wire [3:0] q1;
 
-	counter_2clock C_1(
+	counter_4bit_2clock C_1(
 		clk0, 
 		q0, 
 		rst0);
 
-	counter_2clock C_1(
+	counter_4bit_2clock C_1(
 		clk1, 
 		q1, 
 		rst1);