[HDL] Patch dff models used in yosys tech map

2021-04-16 20:48:15 -06:00 · 2021-04-16 20:48:15 -06:00 · 0a15f366cb
parent 16e02ef485
commit 0a15f366cb
1 changed files with 1 additions and 1 deletions
--- a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
+++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
@ -62,4 +62,4 @@ module  \$_DFFE_NP0P_ (D, C, E, R, Q);
    output Q;
    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
    dffre  #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
-endmodule
+endmodule