Adding Yosys+Verific support.
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@ -109,8 +109,20 @@ General Arguments
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.. option:: --yosys_tmpl <yosys_template_file>
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This option allows the user to provide a custom Yosys template
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While running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_FILE`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables, which can be used as ``${var_name}``. Alternately, user can create a copy and modify according to their need.
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This option allows the user to provide a custom Yosys template while running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Alternately, user can create a copy and modify according to their need. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_FILE`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables. In case if ``--verific`` option is provided then ``ADD_INCLUDE_DIR``, ``ADD_LIBRARY_DIR``, ``ADD_BLACKBOX_MODULES``, ``READ_HDL_FILE`` (should be used instead of ``READ_VERILOG_FILE``) and ``READ_LIBRARY`` additional varialbes are supported. The variables can be used as ``${var_name}``.
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.. option:: --ys_rewrite_tmpl <yosys_rewrite_template_file>
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This option allows the user to provide an alternate Yosys template to rewrite Verilog netlist while running a yosys_vpr flow. The alternate Yosys template script supports all of the main Yosys template script variables.
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.. option:: --verific
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This option specifies to use Verific as a frontend for Yosys while running a yosys_vpr flow.
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The following standards are used by default for reading input HDL files:
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* Verilog - ``vlog95``
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* System Verilog - ``sv2012``
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* VHDL - ``vhdl2008``
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The option should be used only with custom Yosys template containing Verific commands.
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.. option:: --debug
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@ -94,7 +94,7 @@ Declaring all the above sections are mandatory.
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General Section
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^^^^^^^^^^^^^^^
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.. option:: fpga_flow==<yosys_vpr|vpr_blif>
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.. option:: fpga_flow=<yosys_vpr|vpr_blif>
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This option defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed.
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@ -118,7 +118,72 @@ General Section
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.. option:: timeout_each_job=<true|false>
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Specifies the timeout for each :ref:`run_fpga_flow` execution. Default is set to ``20 min. ``
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Specifies the timeout for each :ref:`run_fpga_flow` execution. Default is set to ``20 min.``
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.. option:: verific=<true|false>
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Specifies to use Verific as a frontend for Yosys while running a yosys_vpr flow.
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The following standards are used by default for reading input HDL files:
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* Verilog - ``vlog95``
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* System Verilog - ``sv2012``
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* VHDL - ``vhdl2008``
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The option should be used only with custom Yosys template containing Verific commands.
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OpenFPGA_SHELL Sections
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^^^^^^^^^^^^^^^^^^^^^^^
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User can specify OpenFPGA_SHELL options in this section.
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.. option:: verific_include_dir=<include_dir>
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The ``include_dir`` is path to the Verilog/VHDL include directory. If there are multiple paths then they can be
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provided as a comma separated list.
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.. option:: verific_library_dir=<library_dir>
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The ``library_dir`` is path to the Verilog/VHDL library directory. Verific will search in this directory to
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find undefined modules. If there are multiple paths then they can be provided as a comma separated list.
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.. option:: verific_verilog_standard=<-vlog95|-vlog2k>
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The option specifies Verilog language standard to be used while reading the Verilog files.
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.. option:: verific_systemverilog_standard=<-sv2005|-sv2009|-sv2012>
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The option specifies SystemVerilog language standard to be used while reading the SystemVerilog files.
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.. option:: verific_vhdl_standard=<-vhdl87|-vhdl93|-vhdl2k|-vhdl2008>
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The option specifies VHDL language standard to be used while reading the VHDL files.
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.. option:: verific_read_lib_name=<lib_name>
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The option specifies library name where Verilog/SystemVerilog/VHDL files specified by ``verific_read_lib_src`` option will be loaded. This option should be used only with ``verific_read_lib_src`` option.
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.. option:: verific_read_lib_src=<library_src_files>
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The option specifies Verilog/SystemVerilog/VHDL files to be loaded into library specified by ``verific_read_lib_name`` option. The ``library_src_files`` should be the source files names separated by commas. This option should be used only with ``verific_read_lib_name`` option.
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.. option:: verific_search_lib=<lib_name>
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The option specifies library name from where will look up for external definitions while reading HDL files.
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.. option:: yosys_cell_sim_verilog=<verilog_files>
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The option specifies Verilog files which should be separated by comma.
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.. option:: yosys_cell_sim_systemverilog=<systemverilog_files>
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The option specifies SystemVerilog files which should be separated by comma.
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.. option:: yosys_cell_sim_vhdl=<vhdl_files>
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The option specifies VHDL files which should be separated by comma.
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.. option:: yosys_blackbox_modules=<blackbox_modules>
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The option specifies blackbox modules names which should be separated by comma (usually these are the modules defined in files specified with yosys_cell_sim_<verilog/systemverilog/vhdl> option).
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Architectures Sections
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@ -101,6 +101,8 @@ parser.add_argument('--yosys_tmpl', type=str, default=None,
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help="Alternate yosys template, generates top_module.blif")
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parser.add_argument('--ys_rewrite_tmpl', type=str, default=None,
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help="Alternate yosys template, to rewrite verilog netlist")
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parser.add_argument('--verific', action="store_true",
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help="Run yosys with verific enabled")
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parser.add_argument('--disp', action="store_true",
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help="Open display while running VPR")
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parser.add_argument('--debug', action="store_true",
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@ -465,11 +467,7 @@ def clean_up_and_exit(msg, clean=False):
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logger.error("Exiting . . . . . .")
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exit(1)
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def run_yosys_with_abc():
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"""
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Execute yosys with ABC and optional blackbox support
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"""
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def create_yosys_params():
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tree = ET.parse(args.arch_file)
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root = tree.getroot()
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try:
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@ -484,18 +482,105 @@ def run_yosys_with_abc():
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args.K = lut_size
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# Yosys script parameter mapping
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ys_params = script_env_vars["PATH"]
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ys_params["READ_VERILOG_FILE"] = " \n".join([
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for indx in range(0, len(OpenFPGAArgs), 2):
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tmpVar = OpenFPGAArgs[indx][2:].upper()
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ys_params[tmpVar] = OpenFPGAArgs[indx+1]
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if not args.verific:
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ys_params["READ_VERILOG_FILE"] = " \n".join([
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"read_verilog -nolatches " + shlex.quote(eachfile)
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for eachfile in args.benchmark_files])
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else:
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if "ADD_INCLUDE_DIR" not in ys_params:
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ys_params["ADD_INCLUDE_DIR"] = ""
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if "ADD_LIBRARY_DIR" not in ys_params:
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ys_params["ADD_LIBRARY_DIR"] = ""
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if "ADD_BLACKBOX_MODULES" not in ys_params:
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ys_params["ADD_BLACKBOX_MODULES"] = ""
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if "READ_HDL_FILE" not in ys_params:
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ys_params["READ_HDL_FILE"] = ""
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if "READ_LIBRARY" not in ys_params:
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ys_params["READ_LIBRARY"] = ""
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if "VERIFIC_VERILOG_STANDARD" not in ys_params:
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ys_params["VERIFIC_VERILOG_STANDARD"] = "-vlog2k"
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if "VERIFIC_SYSTEMVERILOG_STANDARD" not in ys_params:
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ys_params["VERIFIC_SYSTEMVERILOG_STANDARD"] = "-sv"
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if "VERIFIC_VHDL_STANDARD" not in ys_params:
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ys_params["VERIFIC_VHDL_STANDARD"] = "-vhdl"
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ext_to_standard_map = {
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".v" : ys_params["VERIFIC_VERILOG_STANDARD"],
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".vh" : ys_params["VERIFIC_VERILOG_STANDARD"],
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".verilog" : ys_params["VERIFIC_VERILOG_STANDARD"],
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".vlg" : ys_params["VERIFIC_VERILOG_STANDARD"],
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".sv" : ys_params["VERIFIC_SYSTEMVERILOG_STANDARD"],
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".svh" : ys_params["VERIFIC_SYSTEMVERILOG_STANDARD"],
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".vhd" : ys_params["VERIFIC_VHDL_STANDARD"],
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".vhdl" : ys_params["VERIFIC_VHDL_STANDARD"]
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}
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lib_files = []
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include_dirs = set([os.path.dirname(eachfile) for eachfile in args.benchmark_files])
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if "VERIFIC_INCLUDE_DIR" in ys_params:
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include_dirs.update(ys_params["VERIFIC_INCLUDE_DIR"].split(","))
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if include_dirs and not ys_params["ADD_INCLUDE_DIR"]:
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ys_params["ADD_INCLUDE_DIR"] = "\n".join(["verific -vlog-incdir " +
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shlex.quote(eachdir) for eachdir in include_dirs])
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if "VERIFIC_LIBRARY_DIR" in ys_params:
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ys_params["ADD_LIBRARY_DIR"] = "\n".join(["verific -vlog-libdir " +
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shlex.quote(eachdir) for eachdir in ys_params["VERIFIC_LIBRARY_DIR"].split(",")])
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try:
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if "VERIFIC_READ_LIB_NAME" in ys_params and "VERIFIC_READ_LIB_SRC" in ys_params:
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for name in ys_params["VERIFIC_READ_LIB_SRC"].split(","):
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for eachfile in args.benchmark_files:
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if name in eachfile:
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lib_files.append(eachfile)
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break
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if not lib_files:
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clean_up_and_exit("Failed to locate verific library files")
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filename, file_extension = os.path.splitext(lib_files[0])
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ys_params["READ_LIBRARY"] = " ".join(["verific -work",
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ys_params["VERIFIC_READ_LIB_NAME"], ext_to_standard_map[file_extension]] +
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[shlex.quote(eachfile) for eachfile in lib_files])
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for eachfile in args.benchmark_files:
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if eachfile in lib_files:
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continue
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filename, file_extension = os.path.splitext(eachfile)
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ys_params["READ_HDL_FILE"] += " ".join(["verific",
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"-L " + ys_params["VERIFIC_SEARCH_LIB"] if "VERIFIC_SEARCH_LIB" in ys_params else "",
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ext_to_standard_map[file_extension],
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shlex.quote(eachfile), "\n"])
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except:
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logger.exception("Failed to determine design file type")
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clean_up_and_exit("")
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if "YOSYS_CELL_SIM_VERILOG" in ys_params:
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ys_params["READ_HDL_FILE"] += " ".join(["verific",
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ys_params["VERIFIC_VERILOG_STANDARD"],
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ys_params["YOSYS_CELL_SIM_VERILOG"], "\n"])
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if "YOSYS_CELL_SIM_SYSTEMVERILOG" in ys_params:
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ys_params["READ_HDL_FILE"] += " ".join(["verific",
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ys_params["VERIFIC_SYSTEMVERILOG_STANDARD"],
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ys_params["YOSYS_CELL_SIM_SYSTEMVERILOG"], "\n"])
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if "YOSYS_CELL_SIM_VHDL" in ys_params:
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ys_params["READ_HDL_FILE"] += " ".join(["verific",
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ys_params["VERIFIC_VHDL_STANDARD"],
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ys_params["YOSYS_CELL_SIM_VHDL"], "\n"])
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if "YOSYS_BLACKBOX_MODULES" in ys_params:
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ys_params["ADD_BLACKBOX_MODULES"] = ("blackbox " +
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" ".join(["\\" + mod for mod in ys_params["YOSYS_BLACKBOX_MODULES"].split(",")]))
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ys_params["TOP_MODULE"] = args.top_module
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ys_params["LUT_SIZE"] = lut_size
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ys_params["OUTPUT_BLIF"] = args.top_module+"_yosys_out.blif"
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ys_params["OUTPUT_VERILOG"] = args.top_module+"_output_verilog.v"
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for indx in range(0, len(OpenFPGAArgs), 2):
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tmpVar = OpenFPGAArgs[indx][2:].upper()
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ys_params[tmpVar] = OpenFPGAArgs[indx+1]
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return ys_params
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def run_yosys_with_abc():
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"""
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Execute yosys with ABC and optional blackbox support
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"""
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ys_params = create_yosys_params()
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yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
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cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
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tmpl = Template(open(yosys_template, encoding='utf-8').read())
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@ -705,19 +790,7 @@ def run_rewrite_verilog():
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run_command("Yosys", "yosys_rewrite.log", command)
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else:
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# Yosys script parameter mapping
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ys_rewrite_params = {
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"READ_VERILOG_FILE": " \n".join([
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"read_verilog -nolatches " + shlex.quote(eachfile)
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for eachfile in args.benchmark_files]),
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"TOP_MODULE": args.top_module,
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"OUTPUT_BLIF": args.top_module+"_yosys_out.blif",
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"INPUT_BLIF": args.top_module+".blif",
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"OUTPUT_VERILOG": args.top_module+"_output_verilog.v"
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}
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for indx in range(0, len(OpenFPGAArgs), 2):
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tmpVar = OpenFPGAArgs[indx][2:].upper()
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ys_rewrite_params[tmpVar] = OpenFPGAArgs[indx + 1]
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ys_rewrite_params = create_yosys_params()
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# Split a series of scripts by delim ';'
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# And execute the scripts serially
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logger.info("Yosys rewrite iteration: " + str(iteration_idx))
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with open("yosys_rewrite_" + str(iteration_idx) + ".ys", 'w') as archfile:
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archfile.write(tmpl.safe_substitute(ys_rewrite_params))
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run_command("Run yosys", "yosys_rewrite_output.log",
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run_command("Run yosys", "yosys_rewrite_output_" + str(iteration_idx) + ".log",
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[cad_tools["yosys_path"], "yosys_rewrite_" + str(iteration_idx) + ".ys"])
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@ -398,6 +398,9 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
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if task_gc.get("fpga_flow"):
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command += ["--fpga_flow", task_gc.get("fpga_flow")]
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if task_gc.getboolean("verific"):
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command += ["--verific"]
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if task_gc.get("run_engine") == "openfpga_shell":
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for eachKey in task_OFPGAc.keys():
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command += [f"--{eachKey}",
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