[Arch] Update k4n4 arch with true multi-mode flip-flop
This commit is contained in:
tangxifan
parent
0b6a9b06f5
commit
fd85f956c9
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@ -139,15 +139,15 @@
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<circuit_model type="ff" name="MULTI_MODE_DFFRQ" prefix="MULTI_MODE_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="R" lib_name="RST" size="1" default_val="0"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="C" lib_name="CK" size="1" default_val="0"/>
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<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="0"/>
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</circuit_model>
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<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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@ -220,20 +220,34 @@
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</pb_type>
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<pb_type name="clb.fle" physical_mode_name="physical"/>
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<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
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<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
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<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="MULTI_MODE_DFFRQ"/>
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<!-- Binding operating pb_type to physical pb_type -->
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<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
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<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
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<port name="in" physical_mode_port="in[0:2]"/>
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<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0">
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<port name="clk" physical_mode_port="C"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
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<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
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<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1">
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<port name="RN" physical_mode_port="R"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
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<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
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<port name="in" physical_mode_port="in[0:3]"/>
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<port name="out" physical_mode_port="lut4_out"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
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<pb_type name="clb.fle[n1_lut4].ble4.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
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<port name="clk" physical_mode_port="C"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut4].ble4.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
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<pb_type name="clb.fle[n1_lut4].ble4.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
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<pb_type name="clb.fle[n1_lut4].ble4.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
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<port name="RN" physical_mode_port="R"/>
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</pb_type>
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<!-- End physical pb_type binding in complex block IO -->
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</pb_type_annotations>
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</openfpga_architecture>
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@ -7,11 +7,7 @@
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with optionally registered outputs
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- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
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Details on Modelling:
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Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
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Authors: Jason Luu, Jeff Goeders, Vaughn Betz
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Authors: Xifan Tang
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-->
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<architecture>
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<!--
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@ -54,6 +50,17 @@
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<port name="Q" clock="C"/>
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</output_ports>
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</model>
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<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
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<model name="dffrn">
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<input_ports>
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<port name="D" clock="C"/>
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<port name="RN" clock="C"/>
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<port name="C" is_clock="1"/>
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</input_ports>
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<output_ports>
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<port name="Q" clock="C"/>
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</output_ports>
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</model>
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</models>
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<tiles>
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<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
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@ -348,15 +355,74 @@
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</delay_matrix>
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</pb_type>
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<!-- Define the flip-flop -->
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<pb_type name="ff" blif_model=".subckt dffr" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<pb_type name="ff" num_pb="1">
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<input name="D" num_pins="1"/>
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<input name="R" num_pins="1"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="C"/>
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<T_setup value="66e-12" port="ff.R" clock="C"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="C"/>
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</pb_type>
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<output name="Q" num_pins="1"/>
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<clock name="C" num_pins="1"/>
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<mode name="latch">
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<pb_type name="latch" blif_model=".latch" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="latch.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="latch.D"/>
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<direct name="direct2" input="ff.C" output="latch.clk"/>
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<direct name="direct3" input="latch.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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<mode name="dff">
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<pb_type name="dff" blif_model=".subckt dff" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="dff.D" clock="C"/>
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<T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="dff.D"/>
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<direct name="direct2" input="ff.C" output="dff.C"/>
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<direct name="direct3" input="dff.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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<mode name="dffr">
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<pb_type name="dffr" blif_model=".subckt dffr" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<input name="R" num_pins="1"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="dffr.D" clock="C"/>
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<T_setup value="66e-12" port="dffr.R" clock="C"/>
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<T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="dffr.D"/>
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<direct name="direct2" input="ff.C" output="dffr.C"/>
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<direct name="direct3" input="ff.R" output="dffr.R"/>
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<direct name="direct4" input="dffr.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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<mode name="dffrn">
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<pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<input name="RN" num_pins="1"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="dffrn.D" clock="C"/>
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<T_setup value="66e-12" port="dffrn.RN" clock="C"/>
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<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="dffrn.D"/>
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<direct name="direct2" input="ff.C" output="dffrn.C"/>
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<direct name="direct3" input="ff.R" output="dffrn.RN"/>
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<direct name="direct4" input="dffrn.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
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<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
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@ -417,16 +483,75 @@
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261e-12
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</delay_matrix>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".subckt dffr" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<input name="R" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="C"/>
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<T_setup value="66e-12" port="ff.R" clock="C"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="C"/>
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</pb_type>
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<!-- Define the flip-flop -->
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<pb_type name="ff" num_pb="1">
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<input name="D" num_pins="1"/>
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<input name="R" num_pins="1"/>
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<output name="Q" num_pins="1"/>
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<clock name="C" num_pins="1"/>
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<mode name="latch">
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<pb_type name="latch" blif_model=".latch" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="latch.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="latch.D"/>
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<direct name="direct2" input="ff.C" output="latch.clk"/>
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<direct name="direct3" input="latch.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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<mode name="dff">
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<pb_type name="dff" blif_model=".subckt dff" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="dff.D" clock="C"/>
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<T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="dff.D"/>
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<direct name="direct2" input="ff.C" output="dff.C"/>
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<direct name="direct3" input="dff.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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<mode name="dffr">
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<pb_type name="dffr" blif_model=".subckt dffr" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<input name="R" num_pins="1"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="dffr.D" clock="C"/>
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<T_setup value="66e-12" port="dffr.R" clock="C"/>
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<T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="dffr.D"/>
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<direct name="direct2" input="ff.C" output="dffr.C"/>
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<direct name="direct3" input="ff.R" output="dffr.R"/>
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<direct name="direct4" input="dffr.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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<mode name="dffrn">
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<pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<input name="RN" num_pins="1"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="dffrn.D" clock="C"/>
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<T_setup value="66e-12" port="dffrn.RN" clock="C"/>
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<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="dffrn.D"/>
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<direct name="direct2" input="ff.C" output="dffrn.C"/>
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<direct name="direct3" input="ff.R" output="dffrn.RN"/>
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<direct name="direct4" input="dffrn.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
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<direct name="direct2" input="lut4.out" output="ff.D">
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