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[Test] Patch test case due to the changes in counter benchmarks

This commit is contained in:
tangxifan 2021-07-02 17:57:39 -06:00
parent 64dcdaec61
commit 9f03ecb160
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf
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@ -25,7 +25,7 @@ openfpga_verilog_default_net_type=wire
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v
[SYNTHESIS_PARAM]
bench0_top = counter