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[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches

This commit is contained in:
tangxifan 2021-06-29 18:28:38 -06:00
parent 2c1692e6dc
commit 5f5a03f17f
2 changed files with 0 additions and 3 deletions
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2
openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga
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@ -59,8 +59,6 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

1
openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf
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@ -34,4 +34,3 @@ bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=