[Arch] Patch architecture to be compatible with pin names of DPRAM cell
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@ -200,10 +200,10 @@
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="waddr" size="7"/>
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<port type="input" prefix="raddr" size="7"/>
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<port type="input" prefix="data_in" size="8"/>
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<port type="input" prefix="data_in" lib_name="d_in" size="8"/>
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<port type="input" prefix="wen" size="1"/>
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<port type="input" prefix="ren" size="1"/>
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<port type="output" prefix="data_out" size="8"/>
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<port type="output" prefix="data_out" lib_name="d_out" size="8"/>
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<port type="clock" prefix="clk" size="1"/>
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</circuit_model>
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</circuit_library>
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