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[Arch] Patch architecture to be compatible with pin names of DPRAM cell

This commit is contained in:
tangxifan 2021-04-28 11:28:23 -06:00
parent a571b063b6
commit 117cea295d
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml
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@ -200,10 +200,10 @@
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="waddr" size="7"/>
<port type="input" prefix="raddr" size="7"/>
<port type="input" prefix="data_in" size="8"/>
<port type="input" prefix="data_in" lib_name="d_in" size="8"/>
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="data_out" size="8"/>
<port type="output" prefix="data_out" lib_name="d_out" size="8"/>
<port type="clock" prefix="clk" size="1"/>
</circuit_model>
</circuit_library>