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[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks

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tangxifan 2021-04-24 13:30:46 -06:00
parent ddcdb35b28
commit 272d1fffb7
2 changed files with 66 additions and 0 deletions
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25
openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v Normal file
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//-----------------------------
// 8-bit multiplier
//-----------------------------
module mult_8(
input [0:7] A,
input [0:7] B,
output [0:15] Y
);
assign Y = A * B;
endmodule
//-----------------------------
// 16-bit multiplier
//-----------------------------
module mult_16(
input [0:15] A,
input [0:15] B,
output [0:31] Y
);
assign Y = A * B;
endmodule

41
openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v Normal file
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//-----------------------------
// 8-bit multiplier
//-----------------------------
module mult_8x8 (
input [0:7] A,
input [0:7] B,
output [0:15] Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
mult_8 #() _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.Y (Y) );
endmodule
//-----------------------------
// 16-bit multiplier
//-----------------------------
module mult_16x16 (
input [0:15] A,
input [0:15] B,
output [0:31] Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
mult_16 #() _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.Y (Y) );
endmodule