From 272d1fffb70fb6a02c4eb4d27f28b9b6b2b4a338 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 24 Apr 2021 13:30:46 -0600
Subject: [PATCH] [HDL] Add tech library for architecture using multi-mode
 16-bit DSP blocks

---
 ..._nonLR_caravel_io_skywater130nm_cell_sim.v | 25 +++++++++++
 ...6_nonLR_caravel_io_skywater130nm_dsp_map.v | 41 +++++++++++++++++++
 2 files changed, 66 insertions(+)
 create mode 100644 openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v
 create mode 100644 openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v

diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v
new file mode 100644
index 000000000..d455c79d0
--- /dev/null
+++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v
@@ -0,0 +1,25 @@
+//-----------------------------
+// 8-bit multiplier
+//-----------------------------
+module mult_8(
+  input [0:7] A,
+  input [0:7] B,
+  output [0:15] Y
+);
+
+assign Y = A * B;
+
+endmodule
+
+//-----------------------------
+// 16-bit multiplier
+//-----------------------------
+module mult_16(
+  input [0:15] A,
+  input [0:15] B,
+  output [0:31] Y
+);
+
+assign Y = A * B;
+
+endmodule
diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v
new file mode 100644
index 000000000..035e6f7eb
--- /dev/null
+++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v
@@ -0,0 +1,41 @@
+//-----------------------------
+// 8-bit multiplier
+//-----------------------------
+module mult_8x8 (
+  input [0:7] A,
+  input [0:7] B,
+  output [0:15] Y
+);
+  parameter A_SIGNED = 0;
+  parameter B_SIGNED = 0;
+  parameter A_WIDTH = 0;
+  parameter B_WIDTH = 0;
+  parameter Y_WIDTH = 0;
+
+  mult_8 #() _TECHMAP_REPLACE_ (
+    .A    (A),
+    .B    (B),
+    .Y    (Y) );
+
+endmodule
+
+//-----------------------------
+// 16-bit multiplier
+//-----------------------------
+module mult_16x16 (
+  input [0:15] A,
+  input [0:15] B,
+  output [0:31] Y
+);
+  parameter A_SIGNED = 0;
+  parameter B_SIGNED = 0;
+  parameter A_WIDTH = 0;
+  parameter B_WIDTH = 0;
+  parameter Y_WIDTH = 0;
+
+  mult_16 #() _TECHMAP_REPLACE_ (
+    .A    (A),
+    .B    (B),
+    .Y    (Y) );
+
+endmodule