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[Test] Patch regression test script due to the change of DPRAM test case

This commit is contained in:
tangxifan 2021-04-28 12:45:52 -06:00
parent b72d4bd807
commit 870432e7f1
1 changed files with 4 additions and 4 deletions
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8
openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
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@ -38,11 +38,11 @@ run-task fpga_verilog/adder/hard_adder --debug --show_thread_logs
echo -e "Testing Verilog generation with soft adder chain in CLBs ";
run-task fpga_verilog/adder/soft_adder --debug --show_thread_logs
echo -e "Testing Verilog generation with 16k block RAMs ";
run-task fpga_verilog/bram/dpram16k --debug --show_thread_logs
echo -e "Testing Verilog generation with 1k block RAMs ";
run-task fpga_verilog/bram/dpram1k --debug --show_thread_logs
echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
run-task fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
echo -e "Testing Verilog generation with 1k block RAMs spanning two columns ";
run-task fpga_verilog/bram/wide_dpram1k --debug --show_thread_logs
echo -e "Testing Verilog generation with heterogeneous fabric using 8-bit single-mode multipliers ";
run-task fpga_verilog/dsp/single_mode_mult_8x8 --debug --show_thread_logs