riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[HDL] Temporarily disable WLR func in primitive HDL modeling

This commit is contained in:
tangxifan 2021-09-20 17:07:51 -07:00
parent c84c0d4a3f
commit d36d1ebee2
1 changed files with 1 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
openfpga_flow/openfpga_cell_library/verilog/sram.v
View File

@ -274,9 +274,7 @@ module SRAM_RE(
//----- when wl is enabled, we can read in data from bl
always @(WE or RE or D)
begin
if (1'b1 == RE) begin
data_readback <= Q;
end else if ((1'b1 == D)&&(1'b1 == WE)) begin
if ((1'b1 == D)&&(1'b1 == WE)) begin
//----- Cases to program internal memory bit
//----- case 1: bl = 1, wl = 1, a -> 0
data <= 1'b1;
@ -289,7 +287,6 @@ module SRAM_RE(
// Wire q_reg to Q
assign Q = data;
assign QN = ~data;
assign D = RE ? data_readback : 1'b0;
endmodule