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[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA

This commit is contained in:
tangxifan 2021-03-23 15:30:41 -06:00
parent 35567fb3c3
commit a4bbffd1aa
2 changed files with 32 additions and 0 deletions
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12
openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v Normal file
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//-----------------------------
// 8-bit multiplier
//-----------------------------
module mult_8(
input [0:7] A,
input [0:7] B,
output [0:15] Y
);
assign Y = A * B;
endmodule

20
openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v Normal file
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//-----------------------------
// 8-bit multiplier
//-----------------------------
module mult_8x8 (
input [0:7] A,
input [0:7] B,
output [0:15] Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
mult_8 #() _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.Y (Y) );
endmodule