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[Arch] Patch architecture files using multi-mode DFFs

This commit is contained in:
tangxifan 2021-04-16 19:59:55 -06:00
parent f2f7f010ea
commit 4239bb4e68
2 changed files with 13 additions and 7 deletions
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4
openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
View File

@ -145,9 +145,9 @@
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" default_val="0" is_reset="true"/>
<port type="input" prefix="RST" size="1" default_val="0"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
<port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0"/>
</circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>

16
openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
View File

@ -79,9 +79,13 @@
<site pb_type="clb"/>
</equivalent_sites>
<input name="I" num_pins="12" equivalent="full"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<output name="O" num_pins="8" equivalent="none"/>
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="spread"/>
</tile>
</tiles>
@ -278,7 +282,7 @@
</interconnect>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".dffr" num_pb="2" class="flipflop">
<pb_type name="ff" blif_model=".subckt dffr" num_pb="2">
<input name="D" num_pins="1" port_class="D"/>
<input name="RST" num_pins="1"/>
<output name="Q" num_pins="1" port_class="Q"/>
@ -344,12 +348,13 @@
</delay_matrix>
</pb_type>
<!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".dffr" num_pb="1" class="flipflop">
<pb_type name="ff" blif_model=".subckt dffr" num_pb="1">
<input name="D" num_pins="1" port_class="D"/>
<input name="RST" num_pins="1"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.RST" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
@ -359,7 +364,7 @@
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<direct name="direct3" input="ble3.reset" output="ff[0:0].RST"/>
<direct name="direct4" input="ble3.reset" output="ff[0:0].RST"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
@ -413,7 +418,7 @@
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".dffr" num_pb="1" class="flipflop">
<pb_type name="ff" blif_model=".subckt dffr" num_pb="1">
<input name="D" num_pins="1" port_class="D"/>
<input name="RST" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
@ -461,6 +466,7 @@
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete>
<complete name="resets" input="clb.reset" output="fle[3:0].reset">
</complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.