[Benchmark] Add missing DPRAM module to LU32PEEng
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tangxifan
parent
5fc83ebea3
commit
55d1004cf2
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@ -2763,7 +2763,7 @@ module top_ram (
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assign q = sub_wire0 | dummy;
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wire[32-1:0] dummy;
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assign dummy = junk_output & 32'b0;
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dual_port_ram inst2(
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dual_port_ram_4096x32 inst2(
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.clk (clk),
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.we1(wren),
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.we2(1'b0),
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@ -3290,7 +3290,7 @@ begin // : STATUS_COUNTER
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else if ((wrreq) && (!rdreq) && (status_cnt != 64 ))
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status_cnt <= status_cnt + 1'b1;
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end
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dual_port_ram ram_addr(
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dual_port_ram_rfifo ram_addr(
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.we1 (wrreq) , // write enable
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.we2 (rdreq) , // Read enable
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.addr1 (wr_pointer) , // address_0 input
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@ -3399,7 +3399,7 @@ begin // : STATUS_COUNTER
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status_cnt <= status_cnt + 1'b1;
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end
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assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0];
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dual_port_ram ram_addr(
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dual_port_ram_wfifo ram_addr(
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.we1 (wrreq) , // write enable
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.we2 (rdreq) , // Read enable
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.addr1 (wr_pointer) , // address_0 input
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@ -3473,7 +3473,7 @@ begin // : STATUS_COUNTER
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else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000))
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status_cnt <= status_cnt + 1;
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end
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dual_port_ram ram_addr(
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dual_port_ram_afifo ram_addr(
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.we1 (wrreq) , // write enable
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.we2 (rdreq) , // Read enable
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.addr1 (wr_pointer) , // address_0 input
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@ -3543,7 +3543,7 @@ begin // : STATUS_COUNTER
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else if ((wrreq) && (!rdreq) && (status_cnt != 16 ))
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status_cnt <= status_cnt + 1'b1;
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end
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dual_port_ram ram_addr(
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dual_port_ram_mfifo ram_addr(
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.we1 (wrreq) , // write enable
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.we2 (rdreq) , // Read enable
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.addr1 (wr_pointer) , // address_0 input
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@ -5431,3 +5431,279 @@ module assemble(roundprod, special, y, sign, specialsign,
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rounded[`WIDTH-2:0]);
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endmodule
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//---------------------------------------
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// A dual-port RAM
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// This module is tuned for VTR's benchmarks
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//---------------------------------------
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module dual_port_ram (
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input clk,
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input we1,
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input we2,
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input [`rRAMSIZEWIDTH - 1 : 0] addr1,
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input [`RAMWIDTH - 1 : 0] data1,
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output [`RAMWIDTH - 1 : 0] out1,
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input [`rRAMSIZEWIDTH - 1 : 0] addr2,
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input [`RAMWIDTH - 1 : 0] data2,
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output [`RAMWIDTH - 1 : 0] out2
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);
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reg [`RAMWIDTH - 1 : 0] ram[2**`rRAMSIZEWIDTH - 1 : 0];
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reg [`RAMWIDTH - 1 : 0] data_out1;
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reg [`RAMWIDTH - 1 : 0] data_out2;
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assign out1 = data_out1;
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assign out2 = data_out2;
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// If writen enable 1 is activated,
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// data1 will be loaded through addr1
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// Otherwise, data will be read out through addr1
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always @(posedge clk) begin
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if (we1) begin
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ram[addr1] <= data1;
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end else begin
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data_out1 <= ram[addr1];
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end
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end
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// If writen enable 2 is activated,
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// data1 will be loaded through addr2
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// Otherwise, data will be read out through addr2
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always @(posedge clk) begin
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if (we2) begin
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ram[addr2] <= data2;
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end else begin
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data_out2 <= ram[addr2];
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end
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end
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endmodule
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//---------------------------------------
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// A dual-port RAM 4096x32
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// This module is tuned for VTR's benchmarks
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//---------------------------------------
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module dual_port_ram_4096x32 (
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input clk,
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input we1,
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input we2,
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input [12 - 1 : 0] addr1,
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input [32 - 1 : 0] data1,
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output [32 - 1 : 0] out1,
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input [12 - 1 : 0] addr2,
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input [32 - 1 : 0] data2,
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output [32 - 1 : 0] out2
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);
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reg [32 - 1 : 0] ram[2**12 - 1 : 0];
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reg [32 - 1 : 0] data_out1;
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reg [32 - 1 : 0] data_out2;
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assign out1 = data_out1;
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assign out2 = data_out2;
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// If writen enable 1 is activated,
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// data1 will be loaded through addr1
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// Otherwise, data will be read out through addr1
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always @(posedge clk) begin
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if (we1) begin
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ram[addr1] <= data1;
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end else begin
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data_out1 <= ram[addr1];
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end
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end
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// If writen enable 2 is activated,
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// data1 will be loaded through addr2
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// Otherwise, data will be read out through addr2
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always @(posedge clk) begin
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if (we2) begin
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ram[addr2] <= data2;
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end else begin
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data_out2 <= ram[addr2];
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end
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end
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endmodule
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//---------------------------------------
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// A dual-port RAM rFIFO
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// This module is tuned for VTR's benchmarks
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//---------------------------------------
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module dual_port_ram_rfifo (
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input clk,
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input we1,
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input we2,
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input [`rFIFOSIZEWIDTH - 1 : 0] addr1,
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input [`rFIFOINPUTWIDTH - 1 : 0] data1,
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output [`rFIFOINPUTWIDTH - 1 : 0] out1,
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input [`rFIFOSIZEWIDTH - 1 : 0] addr2,
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input [`rFIFOINPUTWIDTH - 1 : 0] data2,
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output [`rFIFOINPUTWIDTH - 1 : 0] out2
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);
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reg [`rFIFOINPUTWIDTH - 1 : 0] ram[2**`rFIFOSIZEWIDTH - 1 : 0];
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reg [`rFIFOINPUTWIDTH - 1 : 0] data_out1;
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reg [`rFIFOINPUTWIDTH - 1 : 0] data_out2;
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assign out1 = data_out1;
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assign out2 = data_out2;
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// If writen enable 1 is activated,
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// data1 will be loaded through addr1
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// Otherwise, data will be read out through addr1
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always @(posedge clk) begin
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if (we1) begin
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ram[addr1] <= data1;
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end else begin
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data_out1 <= ram[addr1];
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end
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end
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// If writen enable 2 is activated,
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// data1 will be loaded through addr2
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// Otherwise, data will be read out through addr2
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always @(posedge clk) begin
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if (we2) begin
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ram[addr2] <= data2;
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end else begin
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data_out2 <= ram[addr2];
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end
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end
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endmodule
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//---------------------------------------
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// A dual-port RAM wFIFO
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// This module is tuned for VTR's benchmarks
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//---------------------------------------
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module dual_port_ram_wfifo (
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input clk,
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input we1,
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input we2,
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input [`wFIFOSIZEWIDTH - 1 : 0] addr1,
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input [`wFIFOINPUTWIDTH - 1 : 0] data1,
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output [`wFIFOINPUTWIDTH - 1 : 0] out1,
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input [`wFIFOSIZEWIDTH - 1 : 0] addr2,
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input [`wFIFOINPUTWIDTH - 1 : 0] data2,
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output [`wFIFOINPUTWIDTH - 1 : 0] out2
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);
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reg [`wFIFOINPUTWIDTH - 1 : 0] ram[2**`wFIFOSIZEWIDTH - 1 : 0];
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reg [`wFIFOINPUTWIDTH - 1 : 0] data_out1;
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reg [`wFIFOINPUTWIDTH - 1 : 0] data_out2;
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assign out1 = data_out1;
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assign out2 = data_out2;
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// If writen enable 1 is activated,
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// data1 will be loaded through addr1
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// Otherwise, data will be read out through addr1
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always @(posedge clk) begin
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if (we1) begin
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ram[addr1] <= data1;
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end else begin
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data_out1 <= ram[addr1];
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end
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end
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// If writen enable 2 is activated,
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// data1 will be loaded through addr2
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// Otherwise, data will be read out through addr2
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always @(posedge clk) begin
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if (we2) begin
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ram[addr2] <= data2;
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end else begin
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data_out2 <= ram[addr2];
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end
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end
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endmodule
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//---------------------------------------
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// A dual-port RAM wFIFO
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// This module is tuned for VTR's benchmarks
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//---------------------------------------
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module dual_port_ram_afifo (
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input clk,
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input we1,
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input we2,
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input [`aFIFOSIZEWIDTH - 1 : 0] addr1,
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input [`aFIFOWIDTH - 1 : 0] data1,
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output [`aFIFOWIDTH - 1 : 0] out1,
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input [`aFIFOSIZEWIDTH - 1 : 0] addr2,
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input [`aFIFOWIDTH - 1 : 0] data2,
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output [`aFIFOWIDTH - 1 : 0] out2
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);
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reg [`aFIFOWIDTH - 1 : 0] ram[2**`aFIFOSIZEWIDTH - 1 : 0];
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reg [`aFIFOWIDTH - 1 : 0] data_out1;
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reg [`aFIFOWIDTH - 1 : 0] data_out2;
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assign out1 = data_out1;
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assign out2 = data_out2;
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// If writen enable 1 is activated,
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// data1 will be loaded through addr1
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// Otherwise, data will be read out through addr1
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always @(posedge clk) begin
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if (we1) begin
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ram[addr1] <= data1;
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end else begin
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data_out1 <= ram[addr1];
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end
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end
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// If writen enable 2 is activated,
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// data1 will be loaded through addr2
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// Otherwise, data will be read out through addr2
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always @(posedge clk) begin
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if (we2) begin
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ram[addr2] <= data2;
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end else begin
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data_out2 <= ram[addr2];
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end
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end
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endmodule
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//---------------------------------------
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// A dual-port RAM mFIFO
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// This module is tuned for VTR's benchmarks
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//---------------------------------------
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module dual_port_ram_mfifo (
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input clk,
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input we1,
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input we2,
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input [`mFIFOSIZEWIDTH - 1 : 0] addr1,
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input [`mFIFOWIDTH - 1 : 0] data1,
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output [`mFIFOWIDTH - 1 : 0] out1,
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input [`mFIFOSIZEWIDTH - 1 : 0] addr2,
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input [`mFIFOWIDTH - 1 : 0] data2,
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output [`mFIFOWIDTH - 1 : 0] out2
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);
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reg [`mFIFOWIDTH - 1 : 0] ram[2**`mFIFOSIZEWIDTH - 1 : 0];
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reg [`mFIFOWIDTH - 1 : 0] data_out1;
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reg [`mFIFOWIDTH - 1 : 0] data_out2;
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assign out1 = data_out1;
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assign out2 = data_out2;
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// If writen enable 1 is activated,
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// data1 will be loaded through addr1
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// Otherwise, data will be read out through addr1
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always @(posedge clk) begin
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if (we1) begin
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ram[addr1] <= data1;
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end else begin
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data_out1 <= ram[addr1];
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end
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end
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// If writen enable 2 is activated,
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// data1 will be loaded through addr2
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// Otherwise, data will be read out through addr2
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always @(posedge clk) begin
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if (we2) begin
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ram[addr2] <= data2;
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end else begin
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data_out2 <= ram[addr2];
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end
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end
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endmodule
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