[Test] Bug fix in mcnc openfpga shell script

openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga

@@ -37,7 +37,7 @@ repack #--verbose
 
 # Build the bitstream
 #  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
+build_architecture_bitstream --verbose
 
 # Build fabric-dependent bitstream
 build_fabric_bitstream --verbose
@@ -46,9 +46,7 @@ build_fabric_bitstream --verbose
 #  - Enable the use of explicit port mapping in Verilog netlist
 write_fabric_verilog --file ./SRC \
   --explicit_port_mapping \
-  --include_timing \
-  --include_signal_init
-# --support_icarus_simulator
+  --include_timing
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists
@@ -59,16 +57,6 @@ write_fabric_verilog --file ./SRC \
 write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
 write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
 
-# Write the SDC files for PnR backend
-#  - Turn on every options here
-write_pnr_sdc --file ./SDC
-
-# Write SDC to disable timing for configure ports
-write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file ./SDC_analysis
-
 # Finish and exit OpenFPGA
 exit