whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Dan Ravensloft
8b4eb78849
intel_alm: fix DFFE matching
2020-06-11 19:55:51 +02:00
diego
d68a8f9e2b
Removing trailing whitespace
2020-06-10 10:35:40 -05:00
Claire Wolf
b3b515087d
Fix tests/opt/opt_rmdff
...
This only passed before because "prep" was also running opt_rmdff
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 22:48:26 +02:00
diego
3c2a1171ff
Adding latch tests for shift&mask AST dynamic part-select enhancements
2020-06-09 15:17:01 -05:00
Peter Crozier
01ec681373
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 20:34:52 +01:00
Peter Crozier
76c499db71
Support packed arrays in struct/union.
2020-06-07 18:33:11 +01:00
Claire Wolf
7112f187cd
Add missing .gitignore file
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 22:25:47 +02:00
clairexen
352731df4e
Merge pull request #2041 from PeterCrozier/struct
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Implementation of SV structs.
2020-06-04 18:26:07 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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abc9: -dff improvements
2020-06-04 08:15:25 -07:00
Eddie Hung
45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
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abc9: fixes around handling combinatorial loops
2020-06-03 17:35:46 -07:00
Peter Crozier
0d3f7ea011
Merge branch 'master' into struct
2020-06-03 17:19:28 +01:00
Eddie Hung
8a11019d38
tests: tidy up testcase
2020-06-03 08:41:55 -07:00
Eddie Hung
46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings
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tests: reduce test warnings
2020-06-03 08:37:07 -07:00
Miodrag Milanovic
0a88f002e5
allow range for mux test
2020-06-01 13:48:19 +02:00
Eddie Hung
ea4374a223
abc9_ops: update messaging (credit to @Xiretza for spotting)
2020-05-30 08:57:48 -07:00
Eddie Hung
d3b53bc495
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
2020-05-29 17:17:40 -07:00
clairexen
0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
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ast/simplify: don't bitblast async ROMs declared as `logic`
2020-05-29 16:52:11 +02:00
Xiretza
6a2bac21d3
Expand tests/simple/constmuldivmod.v
2020-05-28 22:59:04 +02:00
whitequark
abac0ab28e
Merge pull request #2091 from boqwxp/printattrs
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Add `printattrs` command to print attributes of currently selected objects.
2020-05-28 10:25:34 +00:00
Alberto Gonzalez
6228b10c9f
printattrs: Add test.
2020-05-27 08:00:00 +00:00
Eddie Hung
1dce798dc5
tests: add ecp5 latch testcase with -abc9
2020-05-25 16:39:16 -07:00
Eddie Hung
a7f2ef6d34
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
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xilinx: tidy up cells_sim.v a little
2020-05-25 14:21:10 -07:00
Eddie Hung
08221edbc1
tests: xilinx macc test to have initval, shorten BMC depth for runtime
2020-05-25 10:09:05 -07:00
Eddie Hung
60aa804915
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
Eddie Hung
9c6d216a06
tests: add test for abc9 -dff removing a redundant flop entirely
2020-05-25 08:43:33 -07:00
Eddie Hung
8dd93e389e
tests: add testcase for abc9 -dff preserving flop names
2020-05-25 08:43:33 -07:00
Eddie Hung
95dcd7e785
test: add attribute-before-stmt test from @nakengelhardt
2020-05-25 07:36:53 -07:00
Eddie Hung
1c117ac023
verilog: do not warn for attributes on null statements
2020-05-25 07:36:53 -07:00
Eddie Hung
29d84339bf
tests: add an generate-else test too
2020-05-25 07:36:53 -07:00
Eddie Hung
589775538c
tests: add #2037 testcase
2020-05-25 07:36:53 -07:00
Eddie Hung
33b03ce904
xaiger: add testcase
2020-05-24 08:48:23 -07:00
Eddie Hung
574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
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verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
2020-05-21 11:00:36 -07:00
Marcelina Kościelnicka
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
Eddie Hung
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
Eddie Hung
e7fd8912f0
tests: attributes before task enable
2020-05-14 16:09:41 -07:00
Eddie Hung
73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
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opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
2020-05-14 11:56:22 -07:00
Eddie Hung
13f9d65b6f
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
2020-05-14 10:33:57 -07:00
Eddie Hung
7cd3f4a79b
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
2020-05-14 10:33:56 -07:00
Eddie Hung
722540dbf9
abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
2020-05-14 10:33:56 -07:00
Eddie Hung
5ad3a85288
abc9: test to use box file instead of auto
2020-05-14 10:33:56 -07:00
Eddie Hung
48052ad813
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
2020-05-14 10:33:56 -07:00
Eddie Hung
8d7b3c06b2
abc9: suppress warnings when no compatible + used flop boxes formed
2020-05-14 10:33:56 -07:00
Eddie Hung
cdd250ef16
xilinx: update abc9_dff tests
2020-05-14 10:33:56 -07:00
Eddie Hung
762b6ad74a
xilinx: remove no-longer-relevant test
2020-05-14 10:33:56 -07:00
Eddie Hung
5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042
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verilog: error if no direction given for task arguments, default to input in SV mode
2020-05-14 09:45:54 -07:00
Claire Wolf
140e9a8e06
Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes
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opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
2020-05-14 18:31:16 +02:00
Claire Wolf
ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
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ast: swap range regardless of range_left >= 0
2020-05-14 18:06:18 +02:00
Eddie Hung
56a5b1d2da
test: add another testcase as per @nakengelhardt
2020-05-14 08:36:36 -07:00
Eddie Hung
5be4b00a0d
opt_clean: improve warning message
2020-05-14 00:59:38 -07:00
Eddie Hung
aa4a69f89b
opt_clean: add init test
2020-05-14 00:31:08 -07:00
Eddie Hung
0d2c33f9f4
tests: update/extend task argument tests
2020-05-13 10:11:45 -07:00
Peter Crozier
17f050d3c6
Allow structs within structs.
2020-05-12 17:20:34 +01:00
Peter Crozier
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
Eddie Hung
e5ce5a4fd5
tests: add #2042 testcase
2020-05-11 11:05:19 -07:00
Eddie Hung
b11cf67a81
Setup tests/verilog properly
2020-05-11 10:31:02 -07:00
Eddie Hung
49e64ad492
test: update opt_expr_alu test
2020-05-08 11:12:58 -07:00
Eddie Hung
495acf9815
tests: opt_expr tests that depend on consumex
2020-05-08 11:07:11 -07:00
Peter Crozier
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
Dan Ravensloft
5b779f7f4e
intel_alm: direct LUTRAM cell instantiation
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By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
Claire Wolf
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
Eddie Hung
a299e606f8
Merge pull request #2028 from zachjs/master
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verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00
Zachary Snow
8f9bba1bbf
verilog: allow null gen-if then block
2020-05-06 08:43:02 -04:00
Eddie Hung
004999218f
techlibs/common: more robustness when *_WIDTH = 0
2020-05-05 08:01:27 -07:00
Eddie Hung
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
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verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
whitequark
66d0ed2bcc
ast/simplify: don't bitblast async ROMs declared as `logic`.
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Fixes #2020 .
2020-05-05 04:16:59 +00:00
Eddie Hung
2e911bc806
test: add failing test
2020-05-04 12:18:02 -07:00
Eddie Hung
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
Eddie Hung
ad8e7878f6
tests: add tests for primitives' src
2020-05-04 10:21:47 -07:00
Claire Wolf
5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu
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Fix the other "opt_expr -fine" bug introduced in 213a89558
2020-05-03 11:56:29 +02:00
Eddie Hung
db13852ed6
test: add test for #2014
2020-05-02 14:22:37 -07:00
Eddie Hung
2e78daf1ca
tests: aiger test for wire->start_offset != 0
2020-05-02 10:00:32 -07:00
Claire Wolf
f38d76efbf
Bugfix in partsel.v signed indices test cases
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Claire Wolf
749c2ff84a
Add tests based on the test case from #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Eddie Hung
7f9ecddb7f
Add testcase for #2010
2020-05-01 14:07:33 -07:00
Eddie Hung
7f203cb019
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
Eddie Hung
b5f38f8342
opt_expr: const_xnor replacement to pad Y with 1'b1
2020-04-24 14:13:45 -07:00
Eddie Hung
ebd6fa945d
tests: opt_expr update xnor/xor tests
2020-04-24 11:16:25 -07:00
Eddie Hung
90b71eb84b
opt_expr: do not group by X, more fixes
2020-04-23 18:15:07 -07:00
Eddie Hung
b84415094c
tests: add opt_expr tests
2020-04-23 15:58:36 -07:00
Dan Ravensloft
3d149aff73
intel_alm: work around a Quartus ICE
2020-04-23 11:03:28 +02:00
Eddie Hung
988d47af85
tests: read +/xilinx/cell_sim.v before xilinx_dsp test
2020-04-22 17:50:30 -07:00
Eddie Hung
db09e96dff
test: ice40_dsp test to read +/ice40/cells_sim.v for default params
2020-04-22 16:35:35 -07:00
Eddie Hung
f582eb14af
xilinx: xilinx_dffopt to read cells_sim.v; fix test
2020-04-22 16:25:23 -07:00
Eddie Hung
fa9df06c9d
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
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select: do not select inside black-/white- boxes unless '=' prefix used
2020-04-22 15:35:05 -07:00
Eddie Hung
db27f2f378
Merge pull request #1973 from YosysHQ/eddie/fix1966
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tests: fix various/plugin.sh when PREFIX != /usr/local/share
2020-04-22 10:19:30 -07:00
Eddie Hung
281cd10717
tests: update select black/white-box tests
2020-04-22 10:16:14 -07:00
Eddie Hung
28623f19ee
Merge pull request #1950 from YosysHQ/eddie/design_import
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design: -import to not count black/white-boxes as candidates for top
2020-04-22 09:32:13 -07:00
Eddie Hung
634b5e2d9f
tests: use `yosys-config --datdir` instead of hard-coded
2020-04-22 08:29:45 -07:00
Claire Wolf
c32b4bded5
Merge pull request #1976 from YosysHQ/dave/fix-sim-const
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sim: Fix handling of constant-connected cell inputs at startup
2020-04-22 16:57:34 +02:00
Marcelina Kościelnicka
846c79b312
hierarchy: Convert positional parameters to named.
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Fixes #1821 .
2020-04-21 19:09:00 +02:00
Claire Wolf
9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite
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Improved rewrite code for writing to bit slice
2020-04-21 18:46:52 +02:00
David Shah
abf81c7639
sim: Fix handling of constant-connected cell inputs at startup
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-21 08:58:52 +01:00
Eddie Hung
38ee59184c
tests: remove write_ilang
2020-04-20 15:42:29 -07:00
Eddie Hung
caf4071c8b
Remove '-ignore_unknown_cells' option from 'sat'
2020-04-20 11:58:23 -07:00
Eddie Hung
a1573058e9
Simplify test case script
2020-04-20 11:54:10 -07:00
Eddie Hung
99a0958601
Remove ununsed files
2020-04-20 11:53:48 -07:00
diego
22f440506b
Modifications of tests as per Eddie's request
2020-04-20 12:45:35 -05:00
Eddie Hung
34d8ff8b56
abc9: add testcase reduced from #1970
2020-04-20 09:38:29 -07:00
diego
50581d5a94
Wrong fixed value
2020-04-17 10:15:22 -05:00
Eddie Hung
9eace8f360
design: add test
2020-04-16 12:48:40 -07:00
Eddie Hung
2ddfb61e65
select: add test for not selecting inside black/white boxes
2020-04-16 12:45:04 -07:00
diego
87910732f1
Adding tests for dynamic part select optimisation
2020-04-16 13:31:05 -05:00
Eddie Hung
2623e335cc
tests: add select -unset tests
2020-04-16 10:51:58 -07:00
Eddie Hung
e8a841467f
tests: add design -delete tests
2020-04-16 08:05:18 -07:00
David Shah
2b57c06360
Merge pull request #1943 from YosysHQ/dave/fix-1919
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ast: Fix handling of identifiers in the global scope
2020-04-16 13:48:20 +01:00
Marcelina Kościelnicka
2f8541a92e
opt_expr: Fix X and CO outputs for $alu identity-mapping rules.
2020-04-16 11:48:29 +02:00
David Shah
4d02505820
ast: Fix handling of identifiers in the global scope
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
Eddie Hung
33b0ac9269
Merge pull request #1933 from YosysHQ/eddie/zinit_more
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zinit: handle $__DFFS?E?_[NP][NP][01] too
2020-04-15 08:36:25 -07:00
Claire Wolf
4ee8fc1473
Merge pull request #1930 from YosysHQ/claire/fix1876
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Fix handling of ternary with constant condition
2020-04-15 16:01:19 +02:00
Dan Ravensloft
2e37e62e6b
synth_intel_alm: alternative synthesis for Intel FPGAs
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By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
Eddie Hung
383fe4a4bc
tests: zinit for new types
2020-04-14 13:08:37 -07:00
Marcelina Kościelnicka
6c16fd760b
opt_expr: Add more $alu optimizations.
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Detect the places in the $alu where the carry bit is constant (due to
const A[i] == B[i] ^ BI) and split it into smaller $alu at these points.
Also, make the existing const-carry detection for low bits more generic
(now handles cases where both BI and CI are constant, but not equal to
one another).
Fixes #1912 .
2020-04-14 21:48:13 +02:00
Eddie Hung
e7121cc15c
tests: add testcases from #1876
2020-04-14 12:39:10 -07:00
Marcelina Kościelnicka
7a36728b2f
dffinit: Avoid setting init parameter to zero-length value.
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Fixes #1704 .
2020-04-14 19:52:19 +02:00
whitequark
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl
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support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
Eddie Hung
b75c5bf743
zinit: resolve one more comment by @mwkmwkmwk
2020-04-13 15:25:37 -07:00
Eddie Hung
c6afce7638
zinit: fix review comments from @mwkmwkmwk
2020-04-13 15:16:51 -07:00
Eddie Hung
091297b9ee
tests: zinit on $adff
2020-04-13 14:29:44 -07:00
Eddie Hung
3c5a9411b1
Add testcase for $_DFF_[NP][NP][01]_
2020-04-13 13:16:49 -07:00
Marcelina Kościelnicka
840bb17089
opt_expr: Optimize multiplications with low 0 bits in operands.
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Fixes #1500 .
2020-04-13 16:52:22 +02:00
Xiretza
7f1d83c5db
Add .gitignore to tests/select/
2020-04-12 22:45:45 +02:00
whitequark
93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style
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ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
2020-04-10 14:51:01 +00:00
Eddie Hung
f11dd6e208
tests: add a quick plugin test
2020-04-09 09:45:20 -07:00
Jeff Wang
249876b614
support using previously declared types/localparams/params in package
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(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
Eddie Hung
d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
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"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
2020-04-03 16:28:25 -07:00
Eddie Hung
92d70cafec
+/cmp2lcu.v to work efficiently for fully/partially constant inputs
2020-04-03 14:28:22 -07:00
Eddie Hung
f68d723cdc
Refactor +/cmp2lcu.v into recursive techmap
2020-04-03 14:28:22 -07:00
Eddie Hung
9b63700678
techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu
2020-04-03 14:28:22 -07:00
whitequark
763401fc82
ecp5: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
whitequark
ebee746ad2
ice40: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
Marcin Kościelnicki
2d3753d730
iopadmap: Fix z assignment to inout port
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Fixes #1841 .
2020-04-02 18:15:04 +02:00
Eddie Hung
4ae7f3a8ed
Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor
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opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
2020-04-01 14:17:01 -07:00
Eddie Hung
e79bc45975
Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu
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opt_expr: improve performance on $alu and $sub
2020-04-01 14:11:09 -07:00
Claire Wolf
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
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ast: simplify to fully populate dynamic slicing case transformation
2020-04-01 08:38:14 +02:00
Eddie Hung
1bb5a5215f
Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup
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opt_merge: speedup
2020-03-31 14:50:32 -07:00
Eddie Hung
3df66027e0
Add dynamic slicing Verilog testcase
2020-03-31 11:51:31 -07:00
N. Engelhardt
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope
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Support module/package/interface/block scope for typedef names.
2020-03-30 13:55:39 +02:00
Rupert Swarbrick
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
...
This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
Claire Wolf
590d8eccb7
Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix
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techmap: Fix cell names with _TECHMAP_REPLACE_.*
2020-03-26 19:03:37 +01:00
Peter Crozier
ecc22f7fed
Support module/package/interface/block scope for typedef names.
2020-03-23 20:07:22 +00:00
N. Engelhardt
3e46faa58c
Merge pull request #1763 from boqwxp/issue1762
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Closes #1762 . Adds warnings for `select` arguments not matching any object and for `add` command when no modules selected
2020-03-23 20:14:13 +01:00
Alberto Gonzalez
0da65d498b
Do not warn on empty selection with prefixed `arg_memb`.
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Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-03-23 17:50:11 +00:00
Alberto Gonzalez
ca4e5dd56e
Suppress warnings for empty `select` arguments when `-count` or `-assert-*` options are set.
2020-03-23 17:30:53 +00:00
Alberto Gonzalez
1b333d49ef
Add tests for `select` command warnings.
2020-03-23 17:30:53 +00:00
N. Engelhardt
b86905d952
Merge pull request #1803 from Grazfather/typedef
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Support standard typedef grammar (Fixed)
2020-03-23 13:43:35 +01:00
Marcin Kościelnicki
c2bf11e42a
techmap: Fix cell names with _TECHMAP_REPLACE_.*
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Fixes #1804 .
2020-03-23 11:17:07 +01:00
Peter
6d8d6b402f
Revert typedef tests to standard grammar.
2020-03-22 18:20:46 -07:00
Eddie Hung
6274f0b075
opt_expr: add failing $xnor test
2020-03-20 14:38:50 -07:00
David Shah
fa77fb857b
Add test for abc9+mince issue
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-20 20:35:28 +00:00
Eddie Hung
317c18fc6f
Simplify breaking tests/arch/*/fsm.ys tests
2020-03-20 11:25:17 -07:00
Eddie Hung
81ca776ea4
opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests
2020-03-19 16:59:11 -07:00
Eddie Hung
5e2562f1a2
opt_expr: add $alu tests
2020-03-19 14:57:10 -07:00
Marcin Kościelnicki
e91368a5f4
fsm_extract: Initialize celltypes with full design.
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Fixes #1781 .
2020-03-19 18:51:21 +01:00
N. Engelhardt
e03f725ef2
Merge pull request #1774 from boqwxp/exec
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Add `exec` command to allow running shell commands from inside Yosys scripts
2020-03-19 13:14:43 +01:00
N. Engelhardt
644deb708d
fix argument order for macOS compatibility
2020-03-18 15:11:49 +01:00
Eddie Hung
9f30d7f843
opt_merge: speedup
2020-03-16 12:43:54 -07:00
Alberto Gonzalez
a09b260c01
Add test for `exec` command.
2020-03-16 07:52:58 +00:00
Miodrag Milanović
569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux
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refixed parsing of constant with comment between size and value
2020-03-14 13:34:59 +02:00
Marcus Comstedt
dd562f29e7
Add regression tests for new handling of comments in constants
2020-03-14 11:41:09 +01:00
Miodrag Milanović
faf4ee69de
Merge pull request #1754 from boqwxp/precise_locations
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Set AST node source location in more parser rules.
2020-03-14 11:18:39 +02:00
Miodrag Milanovic
5b73e7c63a
Added back tests for logger
2020-03-13 15:00:18 +01:00
Eddie Hung
3ada82639f
verilog: add test
2020-03-11 06:51:03 -07:00
David Shah
ddcd87b577
Merge pull request #1721 from YosysHQ/dave/tribuf-unused
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deminout: Don't demote inouts with unused bits
2020-03-10 13:51:40 +00:00
Claire Wolf
a7cc4673c3
Fix partsel expr bit width handling and add test case
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-08 16:12:12 +01:00
N. Engelhardt
88494e81f5
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
Eddie Hung
3c2e910bb3
tests: extend tests/arch/run-tests.sh for defines
2020-03-05 08:08:32 -08:00
David Shah
5cae9c6e16
deminout: Don't demote inouts with unused bits
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-04 18:44:38 +00:00
Claire Wolf
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
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Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
Claire Wolf
879124333f
Merge pull request #1519 from YosysHQ/eddie/submod_po
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submod: several bugfixes
2020-03-03 08:19:06 -08:00
Marcelina Kościelnicka
968956badb
iopadmap: Look harder for already-present buffers. ( #1731 )
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iopadmap: Look harder for already-present buffers.
Fixes #1720 .
2020-03-02 21:40:09 +01:00
Eddie Hung
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
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abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
2020-03-02 12:32:27 -08:00
Eddie Hung
5bba9c3640
ast: fixes #1710 ; do not generate RTLIL for unreachable ternary
2020-02-27 16:55:55 -08:00
Eddie Hung
a179d918ec
Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"
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This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
2020-02-27 10:17:29 -08:00
Eddie Hung
f858219c4e
Cleanup tests
2020-02-27 10:17:29 -08:00
Eddie Hung
717fb492b3
Update bug1630.ys to use -lut 4 instead of lut file
2020-02-27 10:17:29 -08:00
Eddie Hung
bc97e64b21
Fix tests/arch/xilinx/fsm.ys to count flops only
2020-02-27 10:17:29 -08:00
Eddie Hung
977262c803
Update simple_abc9 tests
2020-02-27 10:17:29 -08:00
Alberto Gonzalez
f80fe8dc22
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 02:41:08 +00:00
Alberto Gonzalez
2c2f092c90
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 01:39:36 +00:00
Eddie Hung
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
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Improve specify parser
2020-02-21 09:15:17 -08:00
Claire Wolf
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
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Enum support
2020-02-20 18:17:25 +01:00
Eddie Hung
1d401a7991
clean: ignore specify-s inside cells when determining whether to keep
2020-02-19 10:45:10 -08:00
Jeff Wang
d12ba42a74
add attributes for enumerated values in ilang
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- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
2020-02-17 04:42:42 -05:00
Marcin Kościelnicki
cd60f079d6
tests/aiger: Add missing .gitignore
2020-02-15 19:52:21 +01:00
Miodrag Milanović
c7af1b22ba
Merge pull request #1701 from nakengelhardt/rpc-test
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make rpc frontend unix socket test less fragile
2020-02-14 12:06:37 +01:00
Eddie Hung
d20c1dac73
verilog: ignore ranges too without -specify
2020-02-13 17:58:43 -08:00
Eddie Hung
3065d4092e
Fine tune #1699 tests
2020-02-13 15:14:58 -08:00
Eddie Hung
6b58c1820c
verilog: improve specify support when not in -specify mode
2020-02-13 13:27:15 -08:00
Eddie Hung
2e51dc1856
verilog: ignore '&&&' when not in -specify mode
2020-02-13 13:06:13 -08:00
Eddie Hung
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
Eddie Hung
7cfdf4ffa7
verilog: fix $specify3 check
2020-02-13 12:42:04 -08:00
Eddie Hung
ebb11bcea4
iopadmap: move \init attributes from outpad output to its input
2020-02-13 12:05:14 -08:00
N. Engelhardt
c2467fdd55
make rpc frontend unix socket test less fragile
2020-02-13 20:52:22 +01:00
N. Engelhardt
e069259a53
Merge pull request #1679 from thasti/delay-parsing
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Fix crash on wire declaration with delay
2020-02-13 12:01:27 +01:00
Eddie Hung
d4ff5b2d00
Merge pull request #1670 from rodrigomelo9/master
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$readmem[hb] file inclusion is now relative to the Verilog file
2020-02-10 08:31:01 -08:00
Marcin Kościelnicki
89adef352f
xilinx: Add support for LUT RAM on LUT4-based devices.
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There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.
Fixes #1549
2020-02-07 09:03:22 +01:00
Marcin Kościelnicki
d48950d92d
xilinx: Initial support for LUT4 devices.
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Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.
Fixes #1547
2020-02-07 09:03:22 +01:00
whitequark
081d9318bc
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
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This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 16:52:51 +00:00
whitequark
3f4460a186
ice40: match memory inference attribute values case insensitive.
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LSE/Synplify use case insensitive matching.
2020-02-06 14:58:20 +00:00
whitequark
fc28bf55aa
ice40: add support for both 1364.1 and LSE RAM/ROM attributes.
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This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify appear to interpret attribute values insensitive
to case. There is currently no way to do this in Yosys (attrmap
can only change case of attribute names).
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 14:58:20 +00:00
whitequark
29d130dee9
ice40: remove impossible test.
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iCE40 does not have LUTRAM. This was erroneously added in commit
caab66111e
, and tested for BRAM,
essentially a duplicate of the "dpram.ys" test.
2020-02-06 14:58:20 +00:00
Rodrigo Alejandro Melo
9da5936c05
Added 'set -e' into tests/memfile/run-test.sh
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Also added two checks for situations where the execution must fail.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-06 10:45:40 -03:00
Eddie Hung
4c1d3a126d
shiftx2mux: fix select out of bounds
2020-02-05 16:41:09 -08:00
Eddie Hung
505557e93e
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
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opt_merge: discard \init of '$' cells with 'Q' port when merging
2020-02-05 14:56:26 -08:00
Eddie Hung
6eb7e925a1
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux
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techmap LSB-first for compatible $shift/$shiftx cells
2020-02-05 14:55:57 -08:00
Eddie Hung
0b308c6835
abc9_ops: -reintegrate to use derived_type for box_ports
2020-02-05 14:46:48 -08:00
Eddie Hung
b6a1f627b5
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
2020-02-05 10:47:31 -08:00
Eddie Hung
5ebdc0f8e0
Merge pull request #1638 from YosysHQ/eddie/fix1631
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clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-02-05 19:31:18 +01:00
Stefan Biereigel
90c78f1f85
add testcase for #1614
2020-02-03 21:29:54 +01:00
Rodrigo A. Melo
665a967d87
Merge branch 'master' into master
2020-02-03 11:07:51 -03:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. ( #1673 )
2020-02-03 14:57:17 +01:00
Rodrigo Alejandro Melo
313a425bd5
Merge branch 'master' of https://github.com/YosysHQ/yosys
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Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:56:41 -03:00
David Shah
ebe1d7d5ab
sv: More tests for wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
7e741714df
hierarchy: Correct handling of wildcard port connections with default values
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
a210675d71
sv: Add tests for wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
Rodrigo Alejandro Melo
8217f579b7
Removed 'synth' into tests/memfile/run-test.sh
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-02 12:34:27 -03:00
Rodrigo Alejandro Melo
9b49f1bc46
Added content1.dat into tests/memfile
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Modified run-test.sh to use it.
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-02 12:18:34 -03:00
David Shah
9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf
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ast: Add support for $sformatf system function
2020-02-02 14:53:46 +00:00
Rodrigo Alejandro Melo
eaaba6e091
Added tests/memfile to 'make test' with an extra testcase
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 22:44:06 -03:00
Rodrigo Alejandro Melo
43396fae2c
Added a test for the Memory Content File inclusion using $readmemb
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 17:41:10 -03:00
Eddie Hung
136842b1ef
Merge branch 'master' into eddie/submod_po
2020-02-01 02:14:19 -08:00
Miodrag Milanović
71d148bcaa
Merge pull request #1559 from YosysHQ/efinix_test_fix
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Fix for non-deterministic test
2020-01-29 11:18:06 +01:00
Eddie Hung
d004953772
Add "help -all" and "help -celltypes" sanity test
2020-01-28 18:11:34 -08:00
Eddie Hung
a855f23f22
Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
2020-01-28 12:46:18 -08:00
Eddie Hung
7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
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Unpermute LUT ordering for ice40/ecp5/xilinx
2020-01-28 11:55:51 -08:00
Miodrag Milanovic
94191a93dd
Updated test to use assert-max
2020-01-28 18:26:10 +01:00
Claire Wolf
4ddaa70fd6
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning
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sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
2020-01-28 17:40:28 +01:00
N. Engelhardt
086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
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synth_xilinx: error out if tristate without '-iopad'
2020-01-28 17:24:54 +01:00
Eddie Hung
cfb0366a18
Import tests from #1628
2020-01-27 13:56:16 -08:00
Eddie Hung
48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
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Refactor `abc9` pass
2020-01-27 13:29:15 -08:00
Eddie Hung
af8281d2f5
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings
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ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-27 09:54:04 -08:00
Eddie Hung
b178761551
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
Eddie Hung
2d795fb8c0
simple_abc9 tests to discard whitebox before write for sim
2020-01-23 22:07:43 -08:00
Eddie Hung
dca1c806ec
simple_abc9 tests to discard whitebox before write for sim
2020-01-23 19:55:11 -08:00
Eddie Hung
e471b330ac
abc_box_id -> abc9_box_id in test
2020-01-23 19:12:19 -08:00
Eddie Hung
11e50c0e9e
Test for (* keep *)-ed abc9_box_id
2020-01-23 18:56:25 -08:00
Eddie Hung
48aec34e0d
abc_box_id -> abc9_box_id in test
2020-01-23 18:53:14 -08:00
Eddie Hung
5aaa19f1ab
Update tests with reduced area
2020-01-21 16:50:04 -08:00
Eddie Hung
3d9737c1bd
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-21 16:27:40 -08:00
Eddie Hung
8d1b736c4f
Move from +/shiftx2mux.v into +/techmap.v; cleanup
2020-01-21 15:19:41 -08:00
Eddie Hung
7977574995
New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC
2020-01-21 15:19:41 -08:00
Eddie Hung
cd8f55a911
write_xaiger: fix for (* keep *) on flop output
2020-01-21 09:43:04 -08:00
David Shah
22c967e35e
ast: Add support for $sformatf system function
...
Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 21:20:17 +00:00
Eddie Hung
6a163b5ddd
xilinx_dsp: another typo; move xilinx specific test
2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7
ice40_dsp: fix typo
2020-01-17 16:08:04 -08:00
Eddie Hung
5507c328ff
Add #1644 testcase
2020-01-17 15:57:52 -08:00
Eddie Hung
ad6c49fff1
ice40_dsp: add test
2020-01-17 15:38:26 -08:00
Jeff Wang
8ef5c7d48c
scoped enum tests
2020-01-16 18:13:30 -05:00
Jeff Wang
caf35896da
enum in package test
2020-01-16 18:09:03 -05:00
Jeff Wang
febe7706a2
simple enum test
2020-01-16 18:09:03 -05:00
Eddie Hung
2245afa142
More rigorous test
2020-01-16 09:15:42 -08:00
Eddie Hung
03ce2c72bb
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-15 16:42:16 -08:00
Eddie Hung
5918ede9bd
abc9: aAdd test to check $_NOT_s are absorbed
2020-01-15 14:36:05 -08:00
Eddie Hung
e30b6bbbf8
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-01-15 09:51:31 -08:00
Eddie Hung
53a99ade9c
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-14 11:46:56 -08:00
Eddie Hung
61ffd2d199
Merge pull request #1633 from YosysHQ/eddie/fix_autoname
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autoname: do not rename ports
2020-01-14 11:40:54 -08:00
Eddie Hung
9fa0e03cc9
Merge pull request #1632 from YosysHQ/eddie/fix1630
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read_aiger: uniquify wires with $aiger<autoidx> prefix
2020-01-14 11:40:40 -08:00
Miodrag Milanović
9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr
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Export wire properties in EDIF
2020-01-14 19:19:32 +01:00
Eddie Hung
00964e999d
autoname: add testcase with $-prefix-ed port
2020-01-14 10:13:03 -08:00
Eddie Hung
565d349dc9
Add #1630 testcase
2020-01-13 21:27:53 -08:00
Eddie Hung
a6d4ea7463
abc9: respect (* keep *) on cells
2020-01-13 19:21:11 -08:00
Eddie Hung
9ec948f396
write_xaiger: add support and test for (* keep *) on wires
2020-01-13 19:07:55 -08:00
Eddie Hung
ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad
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abc9: add some scripts/options into "scratchpad"
2020-01-13 09:04:20 -08:00
Eddie Hung
ae619ba87a
Add #1626 testcase
2020-01-12 15:21:26 -08:00
Eddie Hung
c063436eea
Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad
2020-01-11 17:02:20 -08:00
Miodrag Milanovic
ccfe1e5909
this one is fine
2020-01-10 15:20:50 +01:00
Miodrag Milanovic
af852a0ea8
Fix tests
2020-01-10 14:48:01 +01:00
Eddie Hung
a10016ccc5
Add abc9 sanity test
2020-01-09 18:17:06 -08:00
Eddie Hung
94ab3791ce
Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs
2020-01-07 15:44:18 -08:00
Eddie Hung
0d3f10d3cc
Add testcases
2020-01-07 11:44:20 -08:00
Eddie Hung
7c878bf397
tests/aiger: write Yosys output
2020-01-07 11:44:03 -08:00
Eddie Hung
3df869cc7c
Add testcase from #1459
2020-01-06 16:22:22 -08:00
Eddie Hung
6e866030c2
Combine tests to check multiple clock domains
2020-01-02 14:38:59 -08:00
Eddie Hung
b454735bea
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-02 12:44:06 -08:00
Eddie Hung
9e5ff30d05
Merge pull request #1606 from YosysHQ/eddie/improve_tests
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Fix a few issues in tests/arch/*
2020-01-01 13:31:46 -08:00
Eddie Hung
52fe1e0c44
Revert insertion of 'reg', leave note behind
2020-01-01 09:05:46 -08:00
Miodrag Milanovic
a1344ec06e
Added a test case
2020-01-01 16:24:30 +01:00
Eddie Hung
713484fa66
Do not do call equiv_opt when no sim model exists
2019-12-31 18:40:30 -08:00
Eddie Hung
a59016b146
Fix warnings
2019-12-31 18:40:11 -08:00
Eddie Hung
c082329af3
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
Eddie Hung
ccc0a740d2
Add some abc9 dff tests
2019-12-31 16:16:05 -08:00
Eddie Hung
0c4be94a02
Add -D DFF_MODE to abc9_map test
2019-12-30 20:13:25 -08:00
Eddie Hung
fc4b8b8991
Remove submod changes
2019-12-30 14:56:14 -08:00
Eddie Hung
405e974fe5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
Miodrag Milanović
c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default
...
Make iopad option default for all xilinx flows
2019-12-30 20:34:31 +01:00
Eddie Hung
c2c74f9bb0
Merge pull request #1599 from YosysHQ/eddie/retry_1588
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Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
2019-12-30 10:01:02 -08:00
Miodrag Milanovic
f9749c202c
Fix new tests
2019-12-28 16:43:19 +01:00
Miodrag Milanovic
8c3de1d4bd
Merge remote-tracking branch 'origin/master' into iopad_default
2019-12-28 16:23:31 +01:00
Miodrag Milanovic
a82c701668
Make test without iopads
2019-12-28 16:22:24 +01:00
Miodrag Milanovic
509da7ed1a
Revert "Fix xilinx tests, when iopads are default"
...
This reverts commit 477e43d921
.
2019-12-28 16:12:45 +01:00
Eddie Hung
011f749ecf
Update resource count
2019-12-28 02:15:11 -08:00
Eddie Hung
d45869855c
Add #1598 testcase
2019-12-27 16:44:57 -08:00
Marcin Kościelnicki
a24596def3
iopadmap: Emit tristate buffers with const OE for some edge cases.
2019-12-25 17:37:58 +01:00
Eddie Hung
2e21aa59a2
Add DSP cascade tests
2019-12-23 14:58:06 -08:00
Marcin Kościelnicki
666c6128a9
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
Miodrag Milanovic
436fea9e69
Addressed review comments
2019-12-21 20:23:23 +01:00
Miodrag Milanovic
477e43d921
Fix xilinx tests, when iopads are default
2019-12-21 13:18:44 +01:00
Eddie Hung
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Eddie Hung
d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531
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verilog: preserve size of $genval$-s in for loops
2019-12-19 12:21:33 -05:00
Eddie Hung
d675f22f4e
Merge pull request #1571 from YosysHQ/eddie/fix_1570
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mem_arst.v: do not redeclare ANSI port
2019-12-19 12:21:22 -05:00
Eddie Hung
b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass
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add a command to read/modify scratchpad contents
2019-12-18 13:55:44 -05:00
Marcin Kościelnicki
f382164d6e
tests/xilinx: fix flaky mux test
2019-12-18 15:53:29 +01:00
Marcin Kościelnicki
a235250403
xilinx: Add xilinx_dffopt pass ( #1557 )
2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
aff6ad1ce0
xilinx: Improve flip-flop handling.
...
This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
2019-12-18 13:43:43 +01:00
Eddie Hung
a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
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xilinx: add LUTRAM rules for RAM32M, RAM64M
2019-12-16 21:48:21 -08:00
Eddie Hung
aed67dd020
abc9 needs a clean afterwards
2019-12-16 18:42:23 -08:00
Eddie Hung
378d9e6e0c
Add another test
2019-12-16 13:57:55 -08:00
Eddie Hung
db0003410f
Accidentally commented out tests
2019-12-16 13:31:47 -08:00
Eddie Hung
5a00d5578c
Add unconditional match blocks for force RAM
2019-12-16 13:31:15 -08:00
Eddie Hung
e990c013c5
Merge blockram tests
2019-12-16 13:01:51 -08:00
Diego H
87e21b0122
Fixing compiler warning/issues. Moving test script to the correct place
2019-12-16 10:23:45 -06:00
N. Engelhardt
abcd82daca
add assert option to scratchpad command
2019-12-16 14:00:21 +01:00
Diego H
f3f59910eb
Removing fixed attribute value to !ramstyle rules
2019-12-15 23:51:58 -06:00
Diego H
b35559fc33
Merging attribute rules into a single match block; Adding tests
2019-12-15 23:33:09 -06:00
Eddie Hung
a5764a1236
Disable RAM16X1D test
2019-12-13 10:28:13 -08:00
Eddie Hung
d86d073ad6
Add testcase
2019-12-13 10:26:30 -08:00
Diego H
1c96345587
Renaming BRAM memory tests for the sake of uniformity
2019-12-13 09:33:18 -06:00
Eddie Hung
d0ee4cd88f
Remove extraneous synth_xilinx call
2019-12-12 19:00:26 -08:00
Eddie Hung
01116f0f0a
Add tests for these new models
2019-12-12 18:52:48 -08:00
Eddie Hung
037d1a03df
Add #1460 testcase
2019-12-12 17:49:55 -08:00
Eddie Hung
caab66111e
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
Diego H
751a18d7e9
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
2019-12-12 17:32:58 -06:00
Eddie Hung
bea15b537b
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-12 14:57:17 -08:00
Eddie Hung
47ac1b01e6
Add test
2019-12-12 14:43:13 -08:00
Diego H
e33f407655
Adding a note (TODO) in the memory_params.ys check file
2019-12-12 16:06:46 -06:00
N. Engelhardt
1187e91c2f
add test and make help message more verbose
2019-12-12 20:51:59 +01:00
Diego H
937ec1ee78
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
2019-12-12 13:50:36 -06:00
Eddie Hung
23fcfd0adb
Make SV2017 compliant courtesy of @wsnyder
2019-12-12 07:34:07 -08:00
Eddie Hung
4a80510877
Even more obvious testcase
2019-12-11 23:52:05 -08:00
Eddie Hung
61a1f3f49b
Make testcase clearer with \o having its own init
2019-12-11 23:48:09 -08:00
Eddie Hung
151f7533e8
Add testcase
2019-12-11 16:52:37 -08:00
Eddie Hung
e75ca29b19
Add test: 'Warning: ignoring initial value on non-register: \o'
2019-12-11 11:26:54 -08:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
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Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
2019-12-09 17:38:48 -08:00
Eddie Hung
eff858cd33
unmap $__ICE40_CARRY_WRAPPER in test
2019-12-09 14:20:35 -08:00
Eddie Hung
705e520a52
Add a quick testcase for unknown modules as inout
2019-12-09 13:14:46 -08:00
Eddie Hung
e05372778a
ice40_wrapcarry to really preserve attributes via -unwrap option
2019-12-09 11:48:28 -08:00
Miodrag Milanovic
49c9b63e0f
Fix for non-deterministic test
2019-12-07 11:09:25 +01:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
946d5854c0
Drop keep=0 attributes on SB_CARRY
2019-12-06 17:27:47 -08:00
Jan Kowalewski
dcb30b5f4a
tests: arch: xilinx: Change order of arguments in macc.sh
2019-12-06 09:15:49 +01:00
Eddie Hung
d8fbf88980
Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER
2019-12-05 07:01:02 -08:00
Eddie Hung
19bc429482
abc9_map.v to transform INIT=1 to INIT=0
2019-12-04 21:36:41 -08:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. ( #1527 )
...
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
2019-12-04 08:44:08 +01:00
Eddie Hung
67f1ce2d43
Check SB_CARRY name also preserved
2019-12-03 14:51:39 -08:00
Eddie Hung
8de17877d4
Add testcase
2019-12-03 14:48:00 -08:00
Clifford Wolf
2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit
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Gowin: add and test DFF init values
2019-12-03 08:43:18 -08:00
Pepijn de Vos
a7d34a7cb5
update test
2019-12-03 16:56:15 +01:00
Pepijn de Vos
a3b25b4af8
Use -match-init to not synth contradicting init values
2019-12-03 15:12:25 +01:00
David Shah
e9ce4e658b
abc9: Fix breaking of SCCs
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Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 20:44:56 +00:00
Eddie Hung
c61186dd9d
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 13:24:03 -08:00
Eddie Hung
ff1e357682
Add multiple driver testcase
2019-11-27 13:22:26 -08:00
Eddie Hung
4bac6b13be
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 10:17:10 -08:00
Eddie Hung
6464dc35ec
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
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xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
2019-11-27 08:00:22 -08:00
Clifford Wolf
f43c0bd8ba
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
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opt_share: Fix handling of fine cells.
2019-11-27 11:23:16 +01:00
Eddie Hung
f6c0ec1d09
Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
2019-11-27 01:03:33 -08:00
Eddie Hung
6338615aa1
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 01:02:16 -08:00
Eddie Hung
8c813632b6
Revert "submod to bitty rather bussy, for bussy wires used as input and output"
...
This reverts commit cba3073026
.
2019-11-27 00:48:22 -08:00
Eddie Hung
6318e3ce6d
Fix wire width
2019-11-26 23:38:49 -08:00
Eddie Hung
de3476cc23
No need for -abc9
2019-11-26 23:08:14 -08:00
Marcin Kościelnicki
fdcbda195b
opt_share: Fix handling of fine cells.
...
Fixes #1525 .
2019-11-27 08:01:07 +01:00
Eddie Hung
4a0198128e
Add citation
2019-11-26 22:51:16 -08:00
Eddie Hung
15042eaf57
Remove notes
2019-11-26 22:41:35 -08:00
Eddie Hung
222e199b73
Add testcase derived from fastfir_dynamictaps benchmark
2019-11-26 21:26:30 -08:00
Eddie Hung
dd317c9280
Add testcase where \init is copied
2019-11-25 16:07:35 -08:00
Eddie Hung
d087024caf
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 12:42:09 -08:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Marcin Kościelnicki
7562e7304e
xilinx: Use INV instead of LUT1 when applicable
2019-11-25 20:40:39 +01:00
Pepijn de Vos
72d03dc910
attempt to fix formatting
2019-11-25 14:50:34 +01:00
Pepijn de Vos
6c79abbf5a
gowin: add and test dff init values
2019-11-25 14:33:21 +01:00
Eddie Hung
b46e636c91
Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff
2019-11-23 08:38:48 -08:00
Eddie Hung
d223e11a72
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 22:28:35 -08:00
Eddie Hung
5cd3d3db0a
Remove redundant flatten
2019-11-22 22:28:10 -08:00
Eddie Hung
08f85e6438
Stray dump
2019-11-22 20:53:48 -08:00
Eddie Hung
2c5dfd802d
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 17:24:45 -08:00
Eddie Hung
4fdcf8f7d7
Add another test with constant driver
2019-11-22 17:23:34 -08:00
Eddie Hung
74ea438136
Add testcase for signal used as part input part output
2019-11-22 16:52:55 -08:00
Eddie Hung
0806b8e398
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 16:50:56 -08:00
Eddie Hung
8779faf789
Cleanup spacing
2019-11-22 16:50:09 -08:00
Eddie Hung
2ef2e2c040
Add testcase
2019-11-22 16:48:11 -08:00
Eddie Hung
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
Eddie Hung
c761fa49b7
Missing endmodule
2019-11-22 12:37:57 -08:00
Clifford Wolf
72d2ef6fd0
Merge pull request #1511 from YosysHQ/dave/always
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sv: Error checking for always_comb, always_latch and always_ff
2019-11-22 15:32:29 +01:00
Marcin Kościelnicki
e110df9c48
gowin: Remove show command from tests.
2019-11-22 14:49:35 +01:00
Eddie Hung
6841e3b1c2
Another sloppy mistake!
2019-11-21 16:33:20 -08:00
Eddie Hung
fe36275234
Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff
2019-11-21 16:32:52 -08:00
Eddie Hung
39fdcb892b
async2sync -> clk2fflogic
2019-11-21 16:27:34 -08:00
Eddie Hung
5a30e3ac3b
Merge branch 'eddie/xaig_dff_adff' into xaig_dff
2019-11-21 16:15:25 -08:00
Eddie Hung
911a152b39
Add test
2019-11-21 16:13:28 -08:00
David Shah
49b670ca38
sv: Add tests for SV always types
...
Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 21:06:28 +00:00
Eddie Hung
cd9e830b67
Add multi clock test
2019-11-20 13:28:55 -08:00
Eddie Hung
1cc106452f
Add a equiv test too
2019-11-19 17:05:14 -08:00
Eddie Hung
90c5ca330c
Add two tests
2019-11-19 16:57:58 -08:00
Clifford Wolf
7ea0a5937b
Merge pull request #1449 from pepijndevos/gowin
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Improvements for gowin support
2019-11-19 17:29:27 +01:00
Marcin Kościelnicki
15232a48af
Fix #1462 , #1480 .
2019-11-19 08:57:39 +01:00
Marcin Kościelnicki
38e72d6e13
Fix #1496 .
2019-11-18 04:16:48 +01:00
Pepijn de Vos
32f0296df1
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
2019-11-16 12:43:17 +01:00
Pepijn de Vos
ab8c521030
fix fsm test with proper clock enable polarity
2019-11-11 17:51:26 +01:00
Miodrag Milanovic
3e0ffe05a7
Fixed tests
2019-11-11 15:41:33 +01:00
Pepijn de Vos
0e5dbc4abc
fix wide luts
2019-11-06 19:48:18 +01:00
Pepijn de Vos
df8390f5df
don't cound exact luts in big muxes; futile and fragile
2019-10-30 14:58:25 +01:00
Pepijn de Vos
903f997391
add tristate buffer and test
2019-10-28 15:18:01 +01:00
Pepijn de Vos
9517525224
do not use wide luts in testcase
2019-10-28 14:40:12 +01:00
Pepijn de Vos
8226f2db0b
ALU sim tweaks
2019-10-24 13:39:43 +02:00
Pepijn de Vos
83fbfe0964
Add some tests
...
Copied from Efinix.
* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
2019-10-21 16:25:15 +02:00
Miodrag Milanovic
190b40341a
fixed error
2019-10-18 13:15:36 +02:00
Miodrag Milanovic
9bd9db56c8
Unify verilog style
2019-10-18 12:50:24 +02:00
Miodrag Milanovic
12383f37b2
Common memory test now shared
2019-10-18 12:33:35 +02:00
Miodrag Milanovic
477702b8c9
Remove not needed tests
2019-10-18 12:20:35 +02:00
Miodrag Milanovic
5603595e5c
Share common tests
2019-10-18 12:19:59 +02:00
Miodrag Milanovic
ab98f2dccf
fix yosys path
2019-10-18 11:18:53 +02:00
Miodrag Milanovic
56f9482675
Fix path to yosys
2019-10-18 11:12:03 +02:00
Miodrag Milanovic
c2ec7ca703
Moved all tests in arch sub directory
2019-10-18 11:06:12 +02:00
Miodrag Milanovic
3c41599ee1
Add async2sync
2019-10-18 11:00:27 +02:00
Miodrag Milanović
b4d7650548
Merge branch 'master' into mmicko/efinix
2019-10-18 10:54:28 +02:00
Miodrag Milanović
66fca65b58
Merge branch 'master' into mmicko/anlogic
2019-10-18 10:53:56 +02:00
Miodrag Milanović
0b0b0cc0d9
Merge branch 'master' into eddie/pr1352
2019-10-18 10:52:50 +02:00
Miodrag Milanovic
b659082e4a
hierarchy - proc reorder
2019-10-18 09:13:06 +02:00
Miodrag Milanovic
46af9a0ff7
hierarchy - proc reorder
2019-10-18 09:06:43 +02:00
Miodrag Milanovic
0d60902fd9
hierarchy - proc reorder
2019-10-18 09:04:02 +02:00
Miodrag Milanovic
e6ad714d20
hierarchy - proc reorder
2019-10-18 08:06:57 +02:00
Miodrag Milanovic
980df499ab
Make equivalence work with latest master
2019-10-17 17:24:53 +02:00
Miodrag Milanovic
b2f0d75807
remove not needed top module
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
1a399c6456
remove not needed top module
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
a198bcdd4f
split muxes synth per type
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
36af102801
Test dffs separetely
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
487b38b124
Split latches into separete tests
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
fba6229718
Fix formatting
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
53bc499a90
Clean verilog code from not used define block
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
d37cd267a5
Removed alu and div_mod test as agreed, ignore generated files
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
a7fbc8c3fe
Test per flip-flop type
2019-10-17 17:10:42 +02:00
Eddie Hung
3b44084320
Add -assert
2019-10-17 17:10:42 +02:00
Eddie Hung
8422ad3e3a
Use built-in async2sync call as per #1417
2019-10-17 17:10:42 +02:00
Eddie Hung
5b7bc3ab85
Update mul test to DSP48E1
2019-10-17 17:10:02 +02:00
Eddie Hung
08bd1816e3
Update area for div_mod
2019-10-17 17:10:02 +02:00
Eddie Hung
a12801843b
Add comment for lack of tristate logic pointing to #1225
2019-10-17 17:10:02 +02:00
Eddie Hung
eded90b6b4
Move $x to end as 7f0eec8
2019-10-17 17:10:02 +02:00
SergeyDegtyar
305672170b
adffs test update (equiv_opt -multiclock)
2019-10-17 17:10:02 +02:00
Sergey
bb70eb977d
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
68f9239c57
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
df6d0b95da
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
c340d54657
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
205f52ffe5
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
df7fe40529
Fix div_mod test
2019-10-17 17:10:02 +02:00
SergeyDegtyar
7bc8f0c2e2
Add comment with expected behavior for latches,tribuf tests;Update adffs test
2019-10-17 17:10:02 +02:00
SergeyDegtyar
489444bcba
Fix latches.ys test
2019-10-17 17:10:02 +02:00
SergeyDegtyar
6331fa5b02
Remove xilinx_ug901 tests (will be moved to yosys-tests)
2019-10-17 17:10:02 +02:00
SergeyDegtyar
757c476f62
Add smoke tests to tests/xilinx
2019-10-17 17:10:02 +02:00
SergeyDegtyar
ca7a58bcc8
Add comments for unproven cells.
2019-10-17 17:08:38 +02:00
SergeyDegtyar
2ae7dec530
Add tests for Xilinx UG901 examples
2019-10-17 17:08:38 +02:00
Clifford Wolf
e84cedfae4
Use "(id)" instead of "id" for types as temporary hack
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-14 05:24:31 +02:00
Eddie Hung
3fb604c75d
Revert "Add test that is expecting to fail"
...
This reverts commit c28d4b8047
.
2019-10-08 12:41:26 -07:00
Eddie Hung
cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427
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Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-08 12:38:29 -07:00
Eddie Hung
4c89a4e642
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync
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async2sync to be called by equiv_opt only when -async2sync given
2019-10-08 10:53:44 -07:00
Eddie Hung
5c68da4150
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-05 09:27:12 -07:00
Miodrag Milanovic
c0fa6f3e1a
Split mux tests per type
2019-10-04 13:05:16 +02:00
Miodrag Milanovic
1b80489486
Split latch check
2019-10-04 13:00:09 +02:00
Miodrag Milanovic
2c3e140246
split rest od ff's
2019-10-04 12:51:45 +02:00
Miodrag Milanovic
3de7889d08
Separate check for ff's types
2019-10-04 12:48:27 +02:00
Miodrag Milanovic
286a272872
Cleaned tests
2019-10-04 12:42:06 +02:00
Miodrag Milanovic
f94dc2c072
Remove not needed tests
2019-10-04 12:41:41 +02:00
Miodrag Milanovic
ef417fb1b3
Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys into mmicko/efinix
2019-10-04 12:20:49 +02:00
Miodrag Milanovic
03a3deec43
Cleanup and formating
2019-10-04 11:09:59 +02:00
Miodrag Milanovic
a5844e3ceb
split latches into separate checks
2019-10-04 11:08:42 +02:00
Miodrag Milanovic
3238ee7d35
check muxes per type
2019-10-04 11:04:18 +02:00
Miodrag Milanovic
91ad3ab717
check ff's separately
2019-10-04 11:00:49 +02:00
Miodrag Milanovic
3d3479b0af
Cleanup top modules and not used defines
2019-10-04 10:57:47 +02:00
Miodrag Milanovic
1435b9bf97
remove alu test
2019-10-04 10:55:13 +02:00
Miodrag Milanovic
b932654964
Merge branch 'SergeyDegtyar/anlogic' of https://github.com/SergeyDegtyar/yosys into mmicko/anlogic
2019-10-04 10:52:16 +02:00
Miodrag Milanovic
7785f23719
Check latches type one by one
2019-10-04 10:31:51 +02:00
Miodrag Milanovic
3358b2f185
Removed top module where not needed
2019-10-04 09:53:54 +02:00
Miodrag Milanovic
3c40c81030
Test muxes synth one by one
2019-10-04 08:52:54 +02:00
Miodrag Milanovic
d6ef9b1a6b
Cleaned verilog code from not used defines
2019-10-04 08:45:58 +02:00
Miodrag Milanovic
abb5a3a44d
Check for MULT18X18D, since that is working now
2019-10-04 08:44:10 +02:00
Miodrag Milanovic
9e8175fc75
Check flops one by one
2019-10-04 08:42:29 +02:00
Miodrag Milanovic
d19f765a58
Removed alu and div_mod tests as agreed
2019-10-04 08:41:53 +02:00
Eddie Hung
045f344038
Use `sat -tempinduct` and comments for why equiv_opt not sufficient
2019-10-03 11:11:50 -07:00
Eddie Hung
bd5889640b
Disable equiv check for ice40 latches
2019-10-03 10:45:53 -07:00
Eddie Hung
5d680590d6
Use equiv_opt -async2sync for xilinx
2019-10-03 10:30:33 -07:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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Add -select option to aigmap
2019-10-03 11:54:04 +02:00
David Shah
9b9d24f15b
sv: Improve tests
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:45 +01:00
David Shah
abc155715d
sv: Add test scripts for typedefs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
af25585170
sv: Add support for memories of a typedef
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
30d2326030
sv: Add support for memory typedefs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
e70e4afb60
sv: Fix typedefs in packages
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
c962951612
sv: Fix typedef parameters
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
f6b5e47e40
sv: Switch parser to glr, prep for typedef
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
Eddie Hung
e9645c7fa7
Fix broken CI, check reset even for constants, trim rstmux
2019-10-02 21:26:26 -07:00
Eddie Hung
e4bd5aaebf
Fix test
2019-10-02 18:12:25 -07:00
Eddie Hung
c6a55d948a
Merge branch 'eddie/fix_sat_init' into eddie/fix1427
2019-10-02 18:07:38 -07:00
Eddie Hung
f6fabc8fda
Update test
2019-10-02 18:03:45 -07:00
Eddie Hung
e730a595ee
Add test
2019-10-02 18:01:41 -07:00
Eddie Hung
c28d4b8047
Add test that is expecting to fail
2019-10-02 14:52:40 -07:00
Eddie Hung
a4f2f7d23c
Extend test with renaming cells with prefix too
2019-10-02 12:43:18 -07:00
Sergey
eb750670e3
run-test.sh Move $x at end of line.
2019-10-01 11:14:12 +03:00
Sergey
e092c4ae6b
Merge branch 'master' into SergeyDegtyar/efinix
2019-10-01 11:04:32 +03:00
Sergey
d99b1e3261
Merge branch 'master' into SergeyDegtyar/anlogic
2019-10-01 10:57:09 +03:00
Sergey
fc56459746
run-test.sh Move $x at end of line.
2019-10-01 10:55:34 +03:00
Eddie Hung
1caaf51492
equiv_opt with -assert
2019-09-30 19:54:59 -07:00
Eddie Hung
f8d5e11aa7
Update resource count for alu.ys
2019-09-30 19:54:04 -07:00
Eddie Hung
369652d4b9
Add test
2019-09-30 17:20:39 -07:00
Eddie Hung
8b239ee707
Add quick test
2019-09-30 15:34:04 -07:00
Eddie Hung
d992858318
Move $x to end as per 7f0eec8
2019-09-30 15:15:14 -07:00
Eddie Hung
eeb86247c5
Update fsm.ys resource count
2019-09-30 15:14:41 -07:00
Eddie Hung
0bbd1b6364
Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys into eddie/pr1352
2019-09-30 14:57:55 -07:00
whitequark
5c5881695d
Merge pull request #1406 from whitequark/connect_rpc
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rpc: new frontend
2019-09-30 17:38:20 +00:00
whitequark
99a7f39084
rpc: new frontend.
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A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.
Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
2019-09-30 15:53:11 +00:00
Eddie Hung
6216e45eda
Add latch test modified from #1363
2019-09-30 12:52:43 +02:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Marcin Kościelnicki
fd0e3a2c43
Fix _TECHMAP_REMOVEINIT_ handling.
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Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396 .
2019-09-27 18:34:12 +02:00
Miodrag Milanovic
7f0eec8270
Change order of parameters, to work on other os
2019-09-27 11:31:55 +02:00
Eddie Hung
a009314597
Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40
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ICE40 tests. adffs test update (equiv_opt -multiclock).
2019-09-25 16:43:24 -07:00
SergeyDegtyar
b66364ada2
Change sync controls to async.
2019-09-25 14:43:26 +03:00
SergeyDegtyar
fc6ebf8268
adffs test update (equiv_opt -multiclock).
2019-09-24 14:55:32 +03:00
Eddie Hung
bcee87a457
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-23 10:58:28 -07:00
SergeyDegtyar
1070f2e90b
Add new tests for Efinix architecture.
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Problems/questions:
- fsm.ys. equiv_opt -assert failed because of unproven cells;
- latches.ys,tribuf.ys - internal cells present;
- memory.ys - sat called with -verify and proof did fail.
2019-09-23 15:51:41 +03:00
SergeyDegtyar
27377c4663
Add new tests for Anlogic architecture
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Problems/questions:
- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
- Internal cell type $_TBUF_ is present.
2019-09-23 12:12:02 +03:00
Eddie Hung
7c8de1dd18
Hell let's add the original #1381 testcase too
2019-09-20 17:58:51 -07:00
Eddie Hung
6258e6a7e2
Add testcase
2019-09-20 17:51:45 -07:00
Eddie Hung
4100825b81
Add more complicated macc testcase
2019-09-19 22:39:15 -07:00
Eddie Hung
2f98f9deee
Add mac.sh and macc_tb.v for testing
2019-09-19 18:08:16 -07:00
Eddie Hung
b88f0f6450
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
2019-09-19 15:47:41 -07:00
Eddie Hung
65fa8adf6c
Format macc.v
2019-09-19 11:02:14 -07:00
Marcin Kościelnicki
c9f9518de4
Added extractinv pass
2019-09-19 04:02:48 +02:00
Eddie Hung
c663a3680b
Remove stat
2019-09-18 12:44:34 -07:00
Eddie Hung
f7dbfef792
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 12:40:21 -07:00
Eddie Hung
b66c99ece0
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
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peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
2019-09-18 12:40:08 -07:00
Eddie Hung
c9fe4d7992
Add .gitignore
2019-09-18 12:11:33 -07:00
Eddie Hung
c3cba7ab93
Refine macc testcase
2019-09-18 12:07:25 -07:00
SergeyDegtyar
5eb91fa69f
Add comment to dpram test about related issue.
2019-09-18 12:16:04 +03:00
SergeyDegtyar
c597c2f2ae
adffs test update (equiv_opt -multiclock). div_mod test fix
2019-09-17 12:19:31 +03:00
Eddie Hung
f492567c87
Oops
2019-09-13 18:19:07 -07:00
Eddie Hung
a2eee9ebef
Add counter-example from @cliffordwolf
2019-09-13 16:41:10 -07:00
Eddie Hung
14d72c39c3
Revert "Make one check $shift(x)? only; change testcase to be 8b"
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This reverts commit e2c2d784c8
.
2019-09-13 16:33:18 -07:00
Eddie Hung
a1123b095c
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-12 12:11:11 -07:00
David Shah
6044fff074
Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock
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Add equiv_opt -multiclock
2019-09-12 12:26:28 +01:00
Eddie Hung
7d644f40ed
Add AREG=2 BREG=2 test
2019-09-11 17:05:47 -07:00
Eddie Hung
c0f26c2da8
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 13:37:11 -07:00
Eddie Hung
bdb5e0f29c
Cope with presence of reset muxes too
2019-09-11 13:36:37 -07:00
Eddie Hung
f46ef47893
Add more tests
2019-09-11 13:22:41 -07:00
Marcin Kościelnicki
f72765090c
Add -match-init option to dff2dffs.
2019-09-11 19:38:20 +02:00
Eddie Hung
6a95ecd41d
Update test with a/b reset
2019-09-11 10:13:13 -07:00
Eddie Hung
36d6db7f8a
Extend test for RSTP and RSTM
2019-09-11 09:09:08 -07:00
David Shah
c43e52d2d7
Add equiv_opt -multiclock
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Signed-off-by: David Shah <dave@ds0.me>
2019-09-11 13:55:59 +01:00
Eddie Hung
fc7008671f
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 00:57:25 -07:00
Eddie Hung
3a8582081e
proc instead of prep
2019-09-11 00:14:06 -07:00
Eddie Hung
6b23c7c227
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 00:07:33 -07:00
Eddie Hung
580faae8ad
Add unsigned case
2019-09-11 00:07:17 -07:00
Eddie Hung
feb3fa65a3
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-11 00:01:31 -07:00