mirror of https://github.com/YosysHQ/yosys.git
sv: Improve tests
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
parent
5501d9090a
commit
9b9d24f15b
|
@ -7,4 +7,4 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
|
|||
if (wen) mem[addr] <= wdata;
|
||||
rdata <= mem[addr];
|
||||
end
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
@ -1,3 +1,3 @@
|
|||
read -sv typedef_memory.sv
|
||||
prep -top top
|
||||
select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
|
||||
select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
|
||||
|
|
|
@ -7,4 +7,4 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
|
|||
if (wen) mem[addr] <= wdata;
|
||||
rdata <= mem[addr];
|
||||
end
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
read -sv typedef_memory_2.sv
|
||||
prep -top top
|
||||
dump
|
||||
select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
|
||||
select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
|
||||
|
|
|
@ -8,4 +8,4 @@ module top;
|
|||
|
||||
always @* assert(a == 8'hAA);
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
@ -19,4 +19,4 @@ module top;
|
|||
`STATIC_ASSERT(int8 == 8'b11111111);
|
||||
`STATIC_ASSERT(ch == 8'b11111111);
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
@ -0,0 +1,23 @@
|
|||
|
||||
typedef logic [3:0] outer_uint4_t;
|
||||
|
||||
module top;
|
||||
|
||||
outer_uint4_t u4_i = 8'hA5;
|
||||
always @(*) assert(u4_i == 4'h5);
|
||||
|
||||
typedef logic [3:0] inner_type;
|
||||
inner_type inner_i1 = 8'h5A;
|
||||
always @(*) assert(inner_i1 == 4'hA);
|
||||
|
||||
if (1) begin: genblock
|
||||
typedef logic [7:0] inner_type;
|
||||
inner_type inner_gb_i = 8'hA5;
|
||||
always @(*) assert(inner_gb_i == 8'hA5);
|
||||
end
|
||||
|
||||
inner_type inner_i2 = 8'h42;
|
||||
always @(*) assert(inner_i2 == 4'h2);
|
||||
|
||||
|
||||
endmodule
|
|
@ -16,4 +16,4 @@ module top;
|
|||
always @* assert(int8 == 8'b11111111);
|
||||
always @* assert(ch == 8'b11111111);
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
Loading…
Reference in New Issue