mirror of https://github.com/YosysHQ/yosys.git
New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC
This commit is contained in:
Eddie Hung
parent
f165a74824
commit
7977574995
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@ -30,3 +30,4 @@ $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
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$(eval $(call add_share_file,share,techlibs/common/cells.lib))
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$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
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$(eval $(call add_share_file,share,techlibs/common/dummy.box))
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$(eval $(call add_share_file,share,techlibs/common/shiftx2mux.v))
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@ -0,0 +1,38 @@
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(* techmap_celltype = /*"$shift*/ "$shiftx" *)
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module _80_shift_shiftx (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
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generate
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genvar i;
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localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH);
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if (B_WIDTH <= CLOG2_Y_WIDTH+1)
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wire _TECHMAP_FAIL_ = 1;
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// In order to perform this optimisation, this $shiftx must
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// only shift in units of Y_WIDTH, which we check by ensuring
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// that the appropriate LSBs of B are zero
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else if (_TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} && _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] != {CLOG2_Y_WIDTH{1'b0}})
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wire _TECHMAP_FAIL_ = 1;
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else begin
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// Halve the size of $shiftx by $mux-ing A according to
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// the LSB of B, after discarding the zeroed bits
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wire [(A_WIDTH+Y_WIDTH)/2-1:0] AA;
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for (i = 0; i < (A_WIDTH/Y_WIDTH); i=i+2)
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assign AA[(i/2)*Y_WIDTH +: Y_WIDTH] = B[CLOG2_Y_WIDTH] ? A[(i+1)*Y_WIDTH +: Y_WIDTH] : A[(i+0)*Y_WIDTH +: Y_WIDTH];
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$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+Y_WIDTH)/2'd2), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B({B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}), .Y(Y));
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end
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endgenerate
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endmodule
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@ -0,0 +1,110 @@
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read_verilog <<EOT
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module sc1 (i1 ,
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i2 ,
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i3 ,
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i4 ,
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i5 ,
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i6 ,
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i7 ,
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i8 ,
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i9 ,
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i10,
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i11,
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i12,
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i13,
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i14,
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i15,
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binary_out,
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encoder_in,
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enable
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);
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input [3:0] i1 ;
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input [3:0] i2 ;
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input [3:0] i3 ;
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input [3:0] i4 ;
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input [3:0] i5 ;
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input [3:0] i6 ;
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input [3:0] i7 ;
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input [3:0] i8 ;
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input [3:0] i9 ;
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input [3:0] i10 ;
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input [3:0] i11 ;
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input [3:0] i12 ;
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input [3:0] i13 ;
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input [3:0] i14 ;
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input [3:0] i15 ;
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output reg [3:0] binary_out ;
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input [3:0] encoder_in ;
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input enable ;
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always @ (*)
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begin
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binary_out = 0;
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if (enable) begin
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case (encoder_in)
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4'h1 : binary_out = i1;
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4'h2 : binary_out = i2;
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4'h3 : binary_out = i3;
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4'h4 : binary_out = i4;
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4'h5 : binary_out = i5;
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4'h6 : binary_out = i6;
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4'h7 : binary_out = i7;
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4'h8 : binary_out = i8;
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4'h9 : binary_out = i9;
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4'ha : binary_out = i10;
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4'hb : binary_out = i11;/*
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4'hc : binary_out = i12;
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4'hd : binary_out = i13;
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4'he : binary_out = i14;
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4'hf : binary_out = i15;*/
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endcase
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end
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end
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endmodule
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EOT
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proc
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pmux2shiftx
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design -save gold
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design -load gold
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techmap
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abc -lut 6
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select -assert-min 17 t:$lut
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design -load gold
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techmap -map +/shiftx2mux.v -map +/techmap.v
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abc -lut 6
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select -assert-count 16 t:$lut
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load gold
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techmap
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abc9 -lut 6
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select -assert-min 17 t:$lut
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design -load gold
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techmap -map +/shiftx2mux.v -map +/techmap.v
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abc9 -lut 6
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select -assert-count 16 t:$lut
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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