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write_xaiger: add support and test for (* keep *) on wires

This commit is contained in:
Eddie Hung 2020-01-13 19:07:55 -08:00
parent 0d2c06ee47
commit 9ec948f396
2 changed files with 30 additions and 7 deletions
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24
backends/aiger/xaiger.cc
View File

@ -156,7 +156,6 @@ struct XAigerWriter
if (wire->get_bool_attribute(ID::keep))
sigmap.add(wire);
for (auto wire : module->wires())
for (int i = 0; i < GetSize(wire); i++)
{
@ -174,10 +173,11 @@ struct XAigerWriter
undriven_bits.insert(bit);
unused_bits.insert(bit);
if (wire->port_input)
bool keep = wire->get_bool_attribute(ID::keep);
if (wire->port_input || keep)
input_bits.insert(bit);
if (wire->port_output) {
if (wire->port_output || keep) {
if (bit != wirebit)
alias_map[wirebit] = bit;
output_bits.insert(wirebit);
@ -209,9 +209,9 @@ struct XAigerWriter
}
if (cell->type == "$__ABC9_FF_" &&
// The presence of an abc9_mergeability attribute indicates
// that we do want to pass this flop to ABC
cell->attributes.count("\\abc9_mergeability"))
// The presence of an abc9_mergeability attribute indicates
// that we do want to pass this flop to ABC
cell->attributes.count("\\abc9_mergeability"))
{
SigBit D = sigmap(cell->getPort("\\D").as_bit());
SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
@ -430,7 +430,17 @@ struct XAigerWriter
for (const auto &bit : output_bits) {
ordered_outputs[bit] = aig_o++;
aig_outputs.push_back(bit2aig(bit));
int aig;
if (input_bits.count(bit)) {
auto it = aig_map.find(bit);
int input_aig = it->second;
aig_map.erase(it);
aig = bit2aig(bit);
aig_map.at(bit) = input_aig;
}
else
aig = bit2aig(bit);
aig_outputs.push_back(aig);
}
for (auto &i : ff_bits) {

13
tests/techmap/abc9.ys
View File

@ -38,3 +38,16 @@ abc9 -lut 4
design -load gold
scratchpad -copy abc9.script.flow3 abc9.script
abc9 -lut 4
design -reset
read_verilog <<EOT
module top(input a, b, output o);
(* keep *) wire w = a & b;
assign o = ~w;
endmodule
EOT
simplemap
equiv_opt -assert abc9 -lut 4
design -load postopt
select -assert-count 2 t:$lut