mirror of https://github.com/YosysHQ/yosys.git
Setup tests/verilog properly
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parent
aafaeb66df
commit
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1
Makefile
1
Makefile
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@ -780,6 +780,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
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+cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT)
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+cd tests/rpc && bash run-test.sh
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+cd tests/memfile && bash run-test.sh
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+cd tests/verilog && bash run-test.sh
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@echo ""
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@echo " Passed \"make test\"."
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@echo ""
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@ -0,0 +1,3 @@
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/*.log
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/*.out
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/run-test.mk
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@ -0,0 +1,20 @@
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#!/usr/bin/env bash
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set -e
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{
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echo "all::"
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for x in *.ys; do
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echo "all:: run-$x"
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echo "run-$x:"
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echo " @echo 'Running $x..'"
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echo " @../../yosys -ql ${x%.ys}.log $x"
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done
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for s in *.sh; do
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if [ "$s" != "run-test.sh" ]; then
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echo "all:: run-$s"
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echo "run-$s:"
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echo " @echo 'Running $s..'"
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echo " @bash $s"
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fi
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done
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} > run-test.mk
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exec ${MAKE:-make} -f run-test.mk
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