Setup tests/verilog properly

This commit is contained in:
Eddie Hung 2020-05-11 10:30:20 -07:00
parent aafaeb66df
commit b11cf67a81
3 changed files with 24 additions and 0 deletions

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@ -780,6 +780,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
+cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT)
+cd tests/rpc && bash run-test.sh
+cd tests/memfile && bash run-test.sh
+cd tests/verilog && bash run-test.sh
@echo ""
@echo " Passed \"make test\"."
@echo ""

3
tests/verilog/.gitignore vendored Normal file
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@ -0,0 +1,3 @@
/*.log
/*.out
/run-test.mk

20
tests/verilog/run-test.sh Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/env bash
set -e
{
echo "all::"
for x in *.ys; do
echo "all:: run-$x"
echo "run-$x:"
echo " @echo 'Running $x..'"
echo " @../../yosys -ql ${x%.ys}.log $x"
done
for s in *.sh; do
if [ "$s" != "run-test.sh" ]; then
echo "all:: run-$s"
echo "run-$s:"
echo " @echo 'Running $s..'"
echo " @bash $s"
fi
done
} > run-test.mk
exec ${MAKE:-make} -f run-test.mk