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Fix tests

This commit is contained in:
Miodrag Milanovic 2020-01-10 14:48:01 +01:00
parent 6888799c75
commit af852a0ea8
3 changed files with 11 additions and 12 deletions
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8
tests/arch/xilinx/add_sub.ys
View File

@ -4,8 +4,8 @@ proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 14 t:LUT2
select -assert-count 6 t:MUXCY
select -assert-count 8 t:XORCY
select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D
stat
select -assert-count 16 t:LUT2
select -assert-count 2 t:CARRY4
select -assert-none t:LUT2 t:CARRY4 %% t:* %D

7
tests/arch/xilinx/counter.ys
View File

@ -5,10 +5,9 @@ flatten
equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDCE
select -assert-count 1 t:INV
select -assert-count 7 t:MUXCY
select -assert-count 8 t:XORCY
select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D
select -assert-count 2 t:CARRY4
select -assert-none t:BUFG t:FDCE t:INV t:CARRY4 %% t:* %D

8
tests/arch/xilinx/fsm.ys
View File

@ -9,11 +9,11 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 4 t:FDRE
select -assert-count 1 t:FDSE
select -assert-count 1 t:LUT2
select -assert-count 3 t:LUT5
select -assert-count 1 t:LUT6
select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
select -assert-count 2 t:LUT3
select -assert-count 4 t:LUT5
select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D