mirror of https://github.com/YosysHQ/yosys.git
proc instead of prep
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@ -54,7 +54,7 @@ module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0]
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endmodule
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EOT
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prep -nokeepdc
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proc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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@ -71,7 +71,7 @@ module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg
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endmodule
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EOT
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prep -nokeepdc
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proc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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