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Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
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commit
574812d9a5
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@ -2228,24 +2228,24 @@ simple_behavioral_stmt:
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behavioral_stmt:
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defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
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non_opt_delay behavioral_stmt |
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simple_behavioral_stmt ';' | ';' |
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hierarchical_id attr {
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attr simple_behavioral_stmt ';' | ';' |
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attr hierarchical_id {
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AstNode *node = new AstNode(AST_TCALL);
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node->str = *$1;
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delete $1;
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node->str = *$2;
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delete $2;
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ast_stack.back()->children.push_back(node);
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ast_stack.push_back(node);
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append_attr(node, $2);
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append_attr(node, $1);
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} opt_arg_list ';'{
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ast_stack.pop_back();
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} |
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TOK_MSG_TASKS attr {
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attr TOK_MSG_TASKS {
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AstNode *node = new AstNode(AST_TCALL);
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node->str = *$1;
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delete $1;
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node->str = *$2;
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delete $2;
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ast_stack.back()->children.push_back(node);
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ast_stack.push_back(node);
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append_attr(node, $2);
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append_attr(node, $1);
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} opt_arg_list ';'{
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ast_stack.pop_back();
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} |
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@ -2342,8 +2342,6 @@ behavioral_stmt:
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ast_stack.pop_back();
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};
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;
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unique_case_attr:
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/* empty */ {
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$$ = false;
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@ -0,0 +1,28 @@
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read_verilog <<EOT
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module top;
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task foo;
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endtask
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always @*
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(* foo *) foo;
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initial
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if (0) $info("bar");
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endmodule
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EOT
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# Since task enables are not an RTLIL object,
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# any attributes on their AST get dropped
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select -assert-none a:* a:src %d
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logger -expect error "syntax error, unexpected ATTR_BEGIN" 1
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design -reset
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read_verilog <<EOT
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module top;
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task foo;
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endtask
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always @*
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foo (* foo *);
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endmodule
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EOT
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