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Cleanup and formating

This commit is contained in:
Miodrag Milanovic 2019-10-04 11:09:59 +02:00
parent a5844e3ceb
commit 03a3deec43
4 changed files with 4 additions and 2 deletions
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2
tests/anlogic/add_sub.ys
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@ -5,5 +5,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:AL_MAP_ADDER
select -assert-count 4 t:AL_MAP_LUT1
select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D
select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D

2
tests/anlogic/counter.ys
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@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 9 t:AL_MAP_ADDER
select -assert-count 8 t:AL_MAP_SEQ
select -assert-none t:SB_CARRY t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D
select -assert-none t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D

1
tests/anlogic/fsm.ys
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@ -11,4 +11,5 @@ select -assert-count 1 t:AL_MAP_LUT2
select -assert-count 5 t:AL_MAP_LUT5
select -assert-count 1 t:AL_MAP_LUT6
select -assert-count 6 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D

1
tests/anlogic/shifter.ys
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@ -6,4 +6,5 @@ equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D