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Cleanup and formating
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@ -5,5 +5,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd top # Constrain all select calls below inside the top module
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select -assert-count 10 t:AL_MAP_ADDER
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select -assert-count 4 t:AL_MAP_LUT1
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select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D
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select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D
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@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module
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select -assert-count 9 t:AL_MAP_ADDER
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select -assert-count 8 t:AL_MAP_SEQ
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select -assert-none t:SB_CARRY t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D
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select -assert-none t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D
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@ -11,4 +11,5 @@ select -assert-count 1 t:AL_MAP_LUT2
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select -assert-count 5 t:AL_MAP_LUT5
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select -assert-count 1 t:AL_MAP_LUT6
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select -assert-count 6 t:AL_MAP_SEQ
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select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D
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@ -6,4 +6,5 @@ equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 8 t:AL_MAP_SEQ
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select -assert-none t:AL_MAP_SEQ %% t:* %D
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