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Change sync controls to async.

This commit is contained in:
SergeyDegtyar 2019-09-25 14:43:26 +03:00
parent fc6ebf8268
commit b66364ada2
2 changed files with 8 additions and 8 deletions
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8
tests/ice40/adffs.v
View File

@ -27,7 +27,7 @@ module dffs
initial begin
q = 0;
end
always @( posedge clk )
always @( posedge clk, posedge pre )
if ( pre )
q <= 1'b1;
else
@ -39,9 +39,9 @@ module ndffnr
initial begin
q = 0;
end
always @( negedge clk )
if ( !clr )
q <= 1'b0;
always @( negedge clk, negedge pre )
if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule

8
tests/ice40/adffs.ys
View File

@ -4,8 +4,8 @@ flatten
equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFNSR
select -assert-count 1 t:SB_DFFNS
select -assert-count 2 t:SB_DFFR
select -assert-count 1 t:SB_DFFSS
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_DFFNSR t:SB_DFFR t:SB_DFFSS t:SB_LUT4 %% t:* %D
select -assert-count 1 t:SB_DFFS
select -assert-count 2 t:SB_LUT4
select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D