riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Update test with a/b reset

This commit is contained in:
Eddie Hung 2019-09-11 10:13:13 -07:00
parent 36d6db7f8a
commit 6a95ecd41d
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
tests/xilinx/macc.v
View File

@ -61,10 +61,12 @@ always @(posedge clk) begin
// Store accumulation result into a register
adder_out <= adder_out + mult_reg;
end
if (rst) begin
if (rst) begin
a_reg <= 0;
b_reg <= 0;
mult_reg <= 0;
adder_out <= 0;
end
end
end
// Output accumulation result