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Add another test with constant driver
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@ -23,3 +23,31 @@ design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -reset
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read_verilog <<EOT
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module top(input a, output [1:0] b);
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(* submod="bar" *) sub s1(a, b[1]);
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assign b[0] = 1'b0;
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endmodule
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module sub(input a, output c);
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assign c = a;
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endmodule
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EOT
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hierarchy -top top
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proc
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design -save gold
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submod
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dump
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flatten
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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