riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add comment for lack of tristate logic pointing to #1225

This commit is contained in:
Eddie Hung 2019-09-30 14:17:59 -07:00 committed by Miodrag Milanovic
parent eded90b6b4
commit a12801843b
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tests/xilinx/tribuf.ys
View File

@ -7,6 +7,6 @@ synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it.
# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
select -assert-count 1 t:$_TBUF_
select -assert-none t:$_TBUF_ %% t:* %D