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@ -45,43 +45,3 @@ module ndffnr
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else
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q <= d;
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endmodule
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module top (
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input clk,
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input clr,
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input pre,
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input a,
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output b,b1,b2,b3
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);
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dffs u_dffs (
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.clk (clk ),
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.clr (clr),
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.pre (pre),
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.d (a ),
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.q (b )
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);
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ndffnr u_ndffnr (
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.clk (clk ),
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.clr (clr),
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.pre (pre),
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.d (a ),
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.q (b1 )
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);
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adff u_adff (
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.clk (clk ),
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.clr (clr),
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.d (a ),
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.q (b2 )
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);
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adffn u_adffn (
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.clk (clk ),
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.clr (clr),
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.d (a ),
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.q (b3 )
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);
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endmodule
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@ -1,9 +1,40 @@
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read_verilog adffs.v
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design -save read
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proc
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flatten
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equiv_opt -multiclock -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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hierarchy -top adff
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 4 t:TRELLIS_FF
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select -assert-count 3 t:LUT4
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cd adff # Constrain all select calls below inside the top module
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select -assert-count 1 t:TRELLIS_FF
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select -assert-none t:TRELLIS_FF %% t:* %D
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design -load read
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proc
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hierarchy -top adffn
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:TRELLIS_FF
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select -assert-count 1 t:LUT4
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select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
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design -load read
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proc
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hierarchy -top dffs
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:TRELLIS_FF
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select -assert-count 1 t:LUT4
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select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
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design -load read
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proc
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hierarchy -top ndffnr
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:TRELLIS_FF
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select -assert-count 1 t:LUT4
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select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
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@ -13,25 +13,3 @@ module dffe
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if ( en )
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q <= d;
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endmodule
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module top (
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input clk,
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input en,
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input a,
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output b,b1,
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);
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dff u_dff (
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.clk (clk ),
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.d (a ),
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.q (b )
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);
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dffe u_ndffe (
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.clk (clk ),
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.en (en),
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.d (a ),
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.q (b1 )
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);
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endmodule
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@ -1,9 +1,19 @@
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read_verilog dffs.v
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hierarchy -top top
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design -save read
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proc
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flatten
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hierarchy -top dff
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:TRELLIS_FF
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:TRELLIS_FF
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select -assert-none t:TRELLIS_FF %% t:* %D
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design -load read
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proc
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hierarchy -top dffe
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:TRELLIS_FF
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select -assert-none t:TRELLIS_FF %% t:* %D
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