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Disable equiv check for ice40 latches

This commit is contained in:
Eddie Hung 2019-10-03 10:45:53 -07:00
parent 7a6dec1cef
commit bd5889640b
1 changed files with 3 additions and 6 deletions
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9
tests/ice40/latches.ys
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@ -1,14 +1,11 @@
read_verilog latches.v
design -save read
proc
async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
flatten
synth_ice40
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
# Can't run any sort of equivalence check because latches are blown to LUTs
#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load read
#design -load preopt
synth_ice40
cd top
select -assert-count 4 t:SB_LUT4