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Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40 

ICE40 tests. adffs test update (equiv_opt -multiclock).
This commit is contained in:
Eddie Hung 2019-09-25 16:43:24 -07:00 committed by GitHub
parent 739c621330 b66364ada2
commit a009314597
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2 changed files with 14 additions and 19 deletions
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20
tests/ice40/adffs.v
View File

@ -22,29 +22,25 @@ module adffn
q <= d;
endmodule
module dffsr
module dffs
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
always @( posedge clk, posedge pre )
if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
module ndffnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
always @( negedge clk, negedge pre )
if ( !pre )
q <= 1'b1;
else
q <= d;
@ -58,7 +54,7 @@ input a,
output b,b1,b2,b3
);
dffsr u_dffsr (
dffs u_dffs (
.clk (clk ),
.clr (clr),
.pre (pre),
@ -66,7 +62,7 @@ dffsr u_dffsr (
.q (b )
);
ndffnsnr u_ndffnsnr (
ndffnr u_ndffnr (
.clk (clk ),
.clr (clr),
.pre (pre),

13
tests/ice40/adffs.ys
View File

@ -1,12 +1,11 @@
read_verilog adffs.v
proc
async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFF
select -assert-count 1 t:SB_DFFN
select -assert-count 2 t:SB_DFFSR
select -assert-count 7 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D
select -assert-count 1 t:SB_DFFNS
select -assert-count 2 t:SB_DFFR
select -assert-count 1 t:SB_DFFS
select -assert-count 2 t:SB_LUT4
select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D