Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1

techlibs/xilinx/xc7_xcu_brams.txt

@@ -73,7 +73,7 @@ bram $__XILINX_RAMB18_TDP
 endbram
 
 match $__XILINX_RAMB36_SDP
-  min bits 4096
+  min bits 1024
   min efficiency 5
   shuffle_enable B
   make_transp
@@ -89,7 +89,7 @@ match $__XILINX_RAMB18_SDP
 endmatch
 
 match $__XILINX_RAMB36_TDP
-  min bits 4096
+  min bits 1024
   min efficiency 5
   shuffle_enable B
   make_transp

tests/arch/common/memory_params.v

@@ -0,0 +1,45 @@
+`default_nettype none
+module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+   (input  wire                      write_enable, clk,
+    input  wire  [DATA_WIDTH-1:0]    data_in,
+    input  wire  [ADDRESS_WIDTH-1:0] address_in,
+    output wire  [DATA_WIDTH-1:0]    data_out);
+
+   localparam WORD  = (DATA_WIDTH-1);
+   localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+   reg [WORD:0] data_out_r;
+   reg [WORD:0] memory [0:DEPTH];
+
+   always @(posedge clk) begin
+      if (write_enable)
+        memory[address_in] <= data_in;
+      data_out_r <= memory[address_in];
+   end
+
+   assign data_out = data_out_r;
+endmodule // sync_ram_sp
+
+
+`default_nettype none
+module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+   (input  wire                      clk, write_enable,
+    input  wire  [DATA_WIDTH-1:0]    data_in,
+    input  wire  [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
+    output wire  [DATA_WIDTH-1:0]    data_out);
+
+   localparam WORD  = (DATA_WIDTH-1);
+   localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+   reg [WORD:0] data_out_r;
+   reg [WORD:0] memory [0:DEPTH];
+
+   always @(posedge clk) begin
+      if (write_enable)
+        memory[address_in_w] <= data_in;
+      data_out_r <= memory[address_in_r];
+   end
+
+   assign data_out = data_out_r;
+endmodule // sync_ram_sdp
+

tests/arch/xilinx/memory_params.ys

@@ -0,0 +1,45 @@
+# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
+read_verilog ../common/memory_params.v
+chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/memory_params.v
+chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/memory_params.v
+chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/memory_params.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+# Anything memory bits < 1024 -> LUTRAM
+design -reset
+read_verilog ../common/memory_params.v
+chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 0 t:RAMB18E1
+select -assert-count 4 t:RAM128X1D
+
+# More than 18K bits and addr <= 36: -> RAMB36E1 
+design -reset
+read_verilog ../common/memory_params.v
+chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB36E1
+