mirror of https://github.com/YosysHQ/yosys.git
intel_alm: direct LUTRAM cell instantiation
By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
This commit is contained in:
Dan Ravensloft
Marcelina Kościelnicka
parent
0610424940
commit
5b779f7f4e
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@ -7,13 +7,13 @@ $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/al
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/arith_alm_map.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_map.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_sim.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
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# RAM
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bramtypes := m10k m20k
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$(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_$(bramtype).txt)))
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$(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_$(bramtype)_map.v)))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab_map.v))
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# Miscellaneous
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/megafunction_bb.v))
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@ -28,4 +28,4 @@ altsyncram #(
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.clock1(CLK1)
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);
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endmodule
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endmodule
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@ -1,20 +1,18 @@
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bram __MISTRAL_MLAB
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init 0 # TODO: Re-enable when I figure out how LUTRAM init works
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abits 5
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dbits 16 @D32x16
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dbits 18 @D32x18
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dbits 20 @D32x20
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groups 2
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ports 1 1
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wrmode 1 0
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# read enable
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enable 1 0
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transp 1 0
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clocks 1 2
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clkpol 1 1
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endbram
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match __MISTRAL_MLAB
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min efficiency 5
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make_outreg
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endmatch
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bram MISTRAL_MLAB
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init 0 # TODO: Re-enable when Yosys remembers the original filename.
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abits 5
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dbits 1
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groups 2
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ports 1 1
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wrmode 1 0
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# write enable
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enable 1 0
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transp 0 0
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clocks 1 0
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clkpol 1 1
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endbram
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match MISTRAL_MLAB
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min efficiency 5
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make_outreg
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endmatch
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@ -1,29 +0,0 @@
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module __MISTRAL_MLAB(CLK1, CLK2, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA);
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parameter CFG_ABITS = 5;
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parameter CFG_DBITS = 20;
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input CLK1, CLK2;
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input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input A1EN;
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output [CFG_DBITS-1:0] B1DATA;
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altsyncram #(
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.operation_mode("dual_port"),
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.ram_block_type("mlab"),
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.widthad_a(CFG_ABITS),
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.width_a(CFG_DBITS),
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.widthad_b(CFG_ABITS),
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.width_b(CFG_DBITS),
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) _TECHMAP_REPLACE_ (
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.address_a(A1ADDR),
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.data_a(A1DATA),
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.wren_a(A1EN),
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.address_b(B1ADDR),
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.q_b(B1DATA),
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.clock0(CLK1),
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.clock1(CLK1),
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);
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endmodule
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@ -106,3 +106,26 @@ input aclr1;
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output eccstatus;
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endmodule
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(* blackbox *)
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module cyclonev_mlab_cell(portaaddr, portadatain, portbaddr, portbdataout, ena0, clk0, clk1);
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parameter logical_ram_name = "";
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parameter logical_ram_depth = 32;
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parameter logical_ram_width = 20;
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parameter mixed_port_feed_through_mode = "new";
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parameter first_bit_number = 0;
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parameter first_address = 0;
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parameter last_address = 31;
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parameter address_width = 5;
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parameter data_width = 1;
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parameter byte_enable_mask_width = 1;
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parameter port_b_data_out_clock = "NONE";
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parameter [639:0] mem_init0 = 640'b0;
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input [address_width-1:0] portaaddr, portbaddr;
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input [data_width-1:0] portadatain;
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output [data_width-1:0] portbdataout;
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input ena0, clk0, clk1;
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endmodule
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@ -0,0 +1,60 @@
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// The MLAB
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// --------
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// In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic
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// Modules (ALMs, see alm_sim.v), the Cyclone V/10GX also contain
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// Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise
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// the memory the ALM uses to store the look-up table data for general usage,
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// producing a 32 address by 20-bit block of memory. MLABs are spread out
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// around the chip, so they can be placed near where they are needed, rather than
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// being comparatively limited in placement for a deep but narrow memory such as
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// the M10K memory block.
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//
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// MLABs are used mainly for shallow but wide memories, such as CPU register
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// files (which have perhaps 32 registers that are comparatively wide (16/32-bit))
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// or shift registers (by using the output of the Nth bit as input for the N+1th
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// bit).
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//
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// Oddly, instead of providing a block 32 address by 20-bit cell, Quartus asks
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// synthesis tools to build MLABs out of 32 address by 1-bit cells, and tries
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// to put these cells in the same MLAB during cell placement. Because of this
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// a MISTRAL_MLAB cell represents one of these 32 address by 1-bit cells, and
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// 20 of them represent a physical MLAB.
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//
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// How the MLAB works
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// ------------------
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// MLABs are poorly documented, so the following information is based mainly
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// on the simulation model and my knowledge of how memories like these work.
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// Additionally, note that the ports of MISTRAL_MLAB are the ones auto-generated
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// by the Yosys `memory_bram` pass, and it doesn't make sense to me to use
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// `techmap` just for the sake of renaming the cell ports.
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//
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// The MLAB can be initialised to any value, but unfortunately Quartus only
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// allows memory initialisation from a file. Since Yosys doesn't preserve input
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// file information, or write the contents of an `initial` block to a file,
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// Yosys can't currently initialise the MLAB in a way Quartus will accept.
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//
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// The MLAB takes in data from A1DATA at the rising edge of CLK1, and if A1EN
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// is high, writes it to the address in A1ADDR. A1EN can therefore be used to
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// conditionally write data to the MLAB.
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//
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// Simultaneously, the MLAB reads data from B1ADDR, and outputs it to B1DATA,
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// asynchronous to CLK1 and ignoring A1EN. If a synchronous read is needed
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// then the output can be fed to embedded flops. Presently, Yosys assumes
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// Quartus will pack external flops into the MLAB, but this is an assumption
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// that needs testing.
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// The vendor sim model outputs 'x for a very short period (a few
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// combinational delta cycles) after each write. This has been omitted from
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// the following model because it's very difficult to trigger this in practice
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// as clock cycles will be much longer than any potential blip of 'x, so the
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// model can be treated as always returning a defined result.
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module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
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reg [31:0] mem = 32'b0;
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always @(posedge CLK1)
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if (A1EN) mem[A1ADDR] <= A1DATA;
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assign B1DATA = mem[B1ADDR];
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endmodule
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@ -1,8 +1,10 @@
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`ifdef cyclonev
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`define LCELL cyclonev_lcell_comb
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`define MLAB cyclonev_mlab_cell
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`endif
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`ifdef cyclone10gx
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`define LCELL cyclone10gx_lcell_comb
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`define MLAB cyclone10gx_mlab_cell
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`endif
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module __MISTRAL_VCC(output Q);
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@ -80,3 +82,40 @@ parameter LUT1 = 16'h0000;
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`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
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endmodule
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module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
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// Here we get to an unfortunate situation. The cell has a mem_init0 parameter,
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// which takes in a hexadecimal string that could be used to initialise RAM.
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// In the vendor simulation models, this appears to work fine, but Quartus,
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// either intentionally or not, forgets about this parameter and initialises the
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// RAM to zero.
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//
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// Because of this, RAM initialisation is presently disabled, but the source
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// used to generate mem_init0 is kept (commented out) in case this gets fixed
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// or an undocumented way to get Quartus to initialise from mem_init0 is found.
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`MLAB #(
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.logical_ram_name("MISTRAL_MLAB"),
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.logical_ram_depth(32),
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.logical_ram_width(1),
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.mixed_port_feed_through_mode("Dont Care"),
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.first_bit_number(0),
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.first_address(0),
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.last_address(31),
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.address_width(5),
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.data_width(1),
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.byte_enable_mask_width(1),
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.port_b_data_out_clock("NONE"),
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// .mem_init0($sformatf("%08x", INIT))
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) _TECHMAP_REPLACE_ (
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.portaaddr(A1ADDR),
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.portadatain(A1DATA),
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.portbaddr(B1ADDR),
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.portbdataout(B1DATA),
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.ena0(A1EN),
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.clk0(CLK1)
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);
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endmodule
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@ -164,6 +164,7 @@ struct SynthIntelALMPass : public ScriptPass {
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run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str()));
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// Misc and common cells
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run("read_verilog -lib +/intel/common/altpll_bb.v");
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@ -190,7 +191,6 @@ struct SynthIntelALMPass : public ScriptPass {
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if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {
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run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt", "(for Cyclone V / Cyclone 10GX)");
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run("techmap -map +/intel_alm/common/lutram_mlab_map.v", "(for Cyclone V / Cyclone 10GX)");
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}
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if (check_label("map_ffram")) {
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@ -0,0 +1,20 @@
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 16 t:MISTRAL_MLAB
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 2 t:MISTRAL_ALUT2
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select -assert-count 8 t:MISTRAL_ALUT3
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select -assert-count 17 t:MISTRAL_FF
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
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