mirror of https://github.com/YosysHQ/yosys.git
Cleaned tests
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@ -52,22 +52,4 @@
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endcase
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end
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endmodule
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module top (
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input clk,
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input rst,
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input a,
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input b,
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output g0,
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output g1
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);
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fsm u_fsm ( .clock(clk),
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.reset(rst),
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.req_0(a),
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.req_1(b),
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.gnt_0(g0),
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.gnt_1(g1));
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endmodule
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@ -1,12 +1,12 @@
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read_verilog fsm.v
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hierarchy -top top
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hierarchy -top fsm
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proc
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flatten
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#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
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#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 6 t:EFX_FF
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@ -9,14 +9,8 @@ in
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always @(posedge clk)
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begin
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`ifndef BUG
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out <= out >> 1;
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out[7] <= in;
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`else
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out <= out << 1;
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out[7] <= in;
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`endif
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end
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endmodule
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@ -2,28 +2,7 @@ module tristate (en, i, o);
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input en;
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input i;
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output reg o;
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`ifndef BUG
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always @(en or i)
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o <= (en)? i : 1'bZ;
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`else
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always @(en or i)
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o <= (en)? ~i : 1'bZ;
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`endif
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endmodule
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module top (
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input en,
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input a,
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output b
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);
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tristate u_tri (
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.en (en ),
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.i (a ),
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.o (b )
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);
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endmodule
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@ -1,12 +1,12 @@
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read_verilog tribuf.v
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hierarchy -top top
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hierarchy -top tristate
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proc
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tribuf
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flatten
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synth
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equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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cd tristate # Constrain all select calls below inside the top module
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#Internal cell type used. Need support it.
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select -assert-count 1 t:$_TBUF_
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select -assert-none t:$_TBUF_ %% t:* %D
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