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Remove not needed tests

This commit is contained in:
Miodrag Milanovic 2019-10-04 12:41:41 +02:00
parent ef417fb1b3
commit f94dc2c072
6 changed files with 0 additions and 75 deletions
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19
tests/efinix/alu.v
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@ -1,19 +0,0 @@
module top (
input clock,
input [31:0] dinA, dinB,
input [2:0] opcode,
output reg [31:0] dout
);
always @(posedge clock) begin
case (opcode)
0: dout <= dinA + dinB;
1: dout <= dinA - dinB;
2: dout <= dinA >> dinB;
3: dout <= $signed(dinA) >>> dinB;
4: dout <= dinA << dinB;
5: dout <= dinA & dinB;
6: dout <= dinA | dinB;
7: dout <= dinA ^ dinB;
endcase
end
endmodule

13
tests/efinix/alu.ys
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@ -1,13 +0,0 @@
read_verilog alu.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 66 t:EFX_ADD
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 32 t:EFX_FF
select -assert-count 605 t:EFX_LUT4
select -assert-none t:EFX_ADD t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D

13
tests/efinix/div_mod.v
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@ -1,13 +0,0 @@
module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x % y;
assign B = x / y;
endmodule

10
tests/efinix/div_mod.ys
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@ -1,10 +0,0 @@
read_verilog div_mod.v
hierarchy -top top
flatten
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 95 t:EFX_ADD
select -assert-count 114 t:EFX_LUT4
select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D

11
tests/efinix/mul.v
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@ -1,11 +0,0 @@
module top
(
input [7:0] x,
input [7:0] y,
output [15:0] A,
);
assign A = x * y;
endmodule

9
tests/efinix/mul.ys
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@ -1,9 +0,0 @@
read_verilog mul.v
hierarchy -top top
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 17 t:EFX_ADD
select -assert-count 149 t:EFX_LUT4
select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D